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TranslationMobile

調(diào)試時間

"debug" in Chinese : vt. (-bugged; -bugging) 1.驅(qū)除 ...
"time" in Chinese : n. 1.時，時間，時日，歲月。 2.時候，時刻；期間； ...
"just-in-time debugging" in Chinese : 實時調(diào)試
"real time debugging routine" in Chinese : 實時調(diào)試程序
"run time debugging aid" in Chinese : 運行時調(diào)試輔助程序
"run time debugging facilities" in Chinese : 運行時調(diào)試功能
"run time debugging language" in Chinese : 運行時調(diào)試語言
"rda run time debugging aid" in Chinese : 運行期間調(diào)試助手
"debugging" in Chinese : 程序調(diào)整; 除去工藝; 堤序; 調(diào)試發(fā)現(xiàn)和去除軟件失效根源的過程。; 調(diào)試 ...
"arithmetic debugging" in Chinese : 運算調(diào)試; 運算排錯
"asynchronous debugging" in Chinese : 異步調(diào)試; 異步排錯
"automatic debugging" in Chinese : 自動查錯; 自動調(diào)試
"automation of debugging" in Chinese : 調(diào)試自動化
"board debugging" in Chinese : 基板調(diào)試
"breakpoint debugging" in Chinese : 斷點調(diào)試

Examples

The trend is to write compilers in high-level languages, because of the reduced amount of programming time and debugging time .
目前傾向使用高級語言編寫編譯程序，因為這減少了大量的編程序和調(diào)程序的時間。
This allows a component creator to ship the visualizer in a dll to be called only at debug time
這樣一來，組件創(chuàng)建者便可以通過僅在調(diào)試時調(diào)用的dll提供可視化工具。
Ensures that all variables are declared and spelled correctly , which reduces debugging time . the
可確保所有變量的聲明方式和拼寫方式均正確無誤，這樣就縮短了調(diào)試時間。
At the same time , the signal integrity about the key circuit is simulated with the hyperlynx software . with which the circuit performation is enhanced , the debugging time and the cost are reduced
并且通過mentorgraphics公司的hyperlynx仿真軟件對電路關(guān)鍵部分的信號完整性進(jìn)行了仿真,以此提高了電路設(shè)計的成功率,縮短了產(chǎn)品設(shè)計調(diào)試周期,減少了成本損失。
The intelligentized indoors communication systems in this paper has assed the system debugging time after time , and used in slap - up dwelling house , which proves fully its rationality and feasibility , it possess the wide market foreground
本文中的智能信息家電系統(tǒng)已經(jīng)過多次系統(tǒng)調(diào)試，并在高檔住宅中使用，充分證明了其合理性和可行性，具有廣闊的市場前景。
Designer can synthesize the pci core and the user ' s logic into an fpga chip , and can do simulation analysis to test the pci core and the user ' s logic . this technique can increase the design and debugging time , develop the capability of the system
設(shè)計者可以將pci用戶邏輯與pcicore集成在一片fpga里，并且可以在頂層通過仿真來驗證pci接口以及用戶邏輯設(shè)計的正確與否，這樣可以大幅度提高調(diào)試速度，縮短開發(fā)周期，提高電路板的集成度和系統(tǒng)的性能。