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design for testability in Chinese

Pronunciation:
How to pronounce "design for testability""design for testability" in a sentence

Translationmobile phoneMobile

  • 可測(cè)試性程式
  • 可測(cè)性設(shè)計(jì)
  • 面向可測(cè)試性設(shè)計(jì)

Examples

  • Board - level design for testability based on jtag
    的板級(jí)可測(cè)試性設(shè)計(jì)
  • Design by contract is an important approach to design for testability of software
    合約式設(shè)計(jì)是一種重要的軟件易測(cè)試性設(shè)計(jì)方法。
  • Design and implementation of a tool supporting contract - based design for testability of components
    基于合約的構(gòu)件易測(cè)試性設(shè)計(jì)支撐工具的設(shè)計(jì)與實(shí)現(xiàn)
  • Design for testability means adjusting the structure of circuit and making the circuit easy to test
    可測(cè)性設(shè)計(jì)即調(diào)整電路的內(nèi)部結(jié)構(gòu),使電路變得易測(cè)。
  • By using design for testability , we can abridge the contriving period and reduce the cost
    對(duì)電路進(jìn)行可測(cè)性設(shè)計(jì),將縮短產(chǎn)品的開(kāi)發(fā)周期、降低產(chǎn)品的開(kāi)發(fā)成本。
  • Often , designing for testability can push the object s api toward a cleaner , more modular state
    通常,用于可測(cè)性的設(shè)計(jì)可以將對(duì)象的api推向一種更清晰更模塊化的狀態(tài)。
  • The subject of this dissertation is the research on the design for testability in the design environment of system on a chip
    本論文的研究課題為片上系統(tǒng)( systemonachip ,簡(jiǎn)稱(chēng)soc )環(huán)境下的可測(cè)性設(shè)計(jì)方法學(xué)研究。
  • This paper presents the design for testability of dspc50 . in chapter one , the mainly - used methods of design for testability are introduced firstly
    第一章首先介紹了幾種主要的可測(cè)性設(shè)計(jì)方法,比較了各自的特點(diǎn),確定了各自的適用范圍。
  • If necessary , our technicians can cooperate with you to design the product , in order to transfer and apply the concepts of the design for testability
    如有必要,我們的技術(shù)人員可以和您合作,共同設(shè)計(jì)開(kāi)發(fā)產(chǎn)品,以便轉(zhuǎn)換和應(yīng)用測(cè)試設(shè)計(jì)理念。
  • In this paper , based on the study of all kinds of technologies and ways of design for testability prevailing currently in the world , a scheme of design for testability is proposed aimed at jx5 microprocessor ’ s features and specified test requirements
    本文深入研究了目前國(guó)際上數(shù)字電路的各種可測(cè)性設(shè)計(jì)技術(shù)和方法,根據(jù)jx5微處理器的特點(diǎn)和其對(duì)測(cè)試的具體需求,提出了一整套jx5微處理器的可測(cè)性設(shè)計(jì)方案。
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