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TranslationMobile

異常處理

"exception" in Chinese : n. 1.例外；除外，除去。 2.【法律】抗告；異議，不 ...
"process" in Chinese : vi. 〔口語〕排隊走，列隊行進〔procession ...
"exception processing descriptor segment" in Chinese : 異常處理描述符段; 異常處理描述符區(qū)段
"exception" in Chinese : n. 1.例外；除外，除去。 2.【法律】抗告；異議，不服，反對。短語和例 ...
"exception or" in Chinese : 例外或
"exception to" in Chinese : 對于...是個例外; 例外情況
"no exception" in Chinese : 沒有例外，無一例外
"with the exception" in Chinese : 除了情況
"with the exception of" in Chinese : 除...外，毫無疑問，毫無異議; 除以外; 除之外; 除此之外; 除了…，除 ...
"with the exception of this" in Chinese : 除此而外
"exception handling exception item" in Chinese : 異常項
"above exception" in Chinese : 無可非議的
"access exception" in Chinese : 存取異常
"addressing exception" in Chinese : 尋址故障; 尋址異常
"an exception" in Chinese : 一次例外

Examples

Shows event exception processing for deadlocks
展示了針對死鎖的事件異常處理。
Exception processing is monitoring for those situations which indicate an abnormal problem , or an unusual situation that warrants attention from the dba
異常處理是對那些會指出反常問題的狀況或者值得dba注意的不尋常狀況的監(jiān)控。
If an exception process occurs or can t complete the transaction with any one of the third party providers , the web service has to make sure to go back to the previous state
如果發(fā)生異常事件或是不能與任一個第三方完成事務， web服務必須保證能回到前一個狀態(tài)。
A series of basic functions are performed in the chapter 4 , includes microengine initialization , packet receive processing , exception process , mac and ip header processing , ip forwarding , and packet transmit processing , etc . these functions build a basic data path for the whole system
第四章中實現(xiàn)一系列最基本的功能，包括微引擎初始化，包接收處理，異常處理， mac及ip頭部處理， ip轉(zhuǎn)發(fā)以及包發(fā)送處理等。這些功能為整個系統(tǒng)建立起一條基本的數(shù)據(jù)通路。
The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu , and dwells on 64 - bit vega cpu characteristic , and details the eda technology and the main flow of asic design , and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation , and details cache architecture and mmu . the master dissertation dwells on virtual address translating into physical address , instruction cache finding address and instruction fetching , too
詳細的闡述了64位vegacpu的特點，闡述了eda技術(shù)和asic設計的主要流程，闡述了vegacpu流水線結(jié)構(gòu)、流水線操作、流水線暫停和異常處理，虛擬指令地址的結(jié)構(gòu)和產(chǎn)生， mmu結(jié)構(gòu)，包括指令tlb結(jié)構(gòu)和虛擬指令地址向物理指令地址的生成流程， cache結(jié)構(gòu)，尋址原理和指令的寫策略，指令高速緩存的尋址原理和結(jié)構(gòu)，以及指令的獲取流程。