- 基片面積
- 排屑槽
- 切屑通道
- chip: n. (摔跤時)用絆腿把對方摔倒的一種技巧。 vt. ( ...
- area: n. 1.面積；平地；地面。 2.空地；〔英國〕地下室前 ...
- chip cross sectional area: 切屑橫截面面積
- chip mounting area: 芯片安裝面積
- silicon chip area: 硅芯片面積
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chip area中文什么意思
- 基片面積
- 排屑槽
- 切屑通道
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例句與用法
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- Circuit design is the basis of design of demultiplexer . speed , power and chip area are the main factors that should be considered in circuit design . every circuit structure has its merits and drawbacks , e . g . cmos logic family has a slower speed , but lower power , smaller area , scfl ( source couple fet logic ) family has a higher speed , but higher power , larger area . we should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors . flip - flop is the fundamental element of demultiplexer , setup time and hold up time are key factors , which influence the speed of circuit , thus the design aim is how to reduce them . in this thesis we place emphasis on the design of scfl latches
速度、功耗、面積是電路設(shè)計要考慮的主要因素，不同的電路形式具有不同的優(yōu)缺點，如cmos互補邏輯電路功耗低，面積小，速度相對較慢； scfl (源極耦合fet邏輯)電路速度高，功耗和面積較大。所以要針對具體設(shè)計需要選用適當?shù)碾娐沸问交蚱浣M合結(jié)構(gòu)，以滿足設(shè)計要求。觸發(fā)器是分接器的基本組成單元，建立時間和保持時間是影響電路速度的關(guān)鍵，所以減小建立時間和保持時間是觸發(fā)器設(shè)計的主要目標，本文著重介紹了scfl鎖存器的設(shè)計和優(yōu)化方法。 - At the logic synthesis stage , we make some research on the principles of logic synthesis at first , then by utilizing tsmc0 . 25um process , choosing the worst case that the workable temperature can be high to 125 degrees centigrade and the supply voltage is as low as 2 . 25v , and introducing the wireload library for effectively simulating delay and power consumption of wire connection , and taking the same clocks as in simulation , the critical path is 15 . 3ns and the chip area is 0 . 395mm2
在進行邏輯綜合時首先對邏輯綜合的原理作了一定的了解，然后利用tsmc的0 . 25 m的工藝庫，工作電壓為2 . 25v ，工作溫度最高可達到125攝氏度的最壞情況下，進行邏輯綜合時引入了wireload庫以便有效的模擬連線所引起的延遲及功耗，采用與模擬時相同的時鐘，關(guān)鍵路徑為15 . 3ns ，芯片面積為0 . 395mm ~ 2 。 - Firstly , based on conventional vq , a fast algorithm named equal - sum block - extending nearest neighbor search ( ebnns ) is presented , which not only can achieve the reconstructed image of full search algorithm but also can greatly reduce both the codeword search ratio and chip area . in order to improve coding efficiency , a new algorithm called correlation - inheritance coding is proposed , which is embedded in conventional vq system to improve compression ratio by re - encoding the indexes
首先，在普通矢量量化基礎(chǔ)上提出了等和值塊擴展最近鄰快速碼字搜索算法( ebnns ) ，該算法在圖像畫質(zhì)達到窮盡搜索算法的前提下，大大降低了碼字搜索率和硬件實現(xiàn)面積；為了提高編碼效率，在相關(guān)性編碼方面，提出了相關(guān)繼承編碼算法，對普通矢量量化后的編碼索引進行無損重編碼。 - The hspice simulation result shows a temperature coefficient of 11 ppm / " c from - 40 ? to 100 ' c and output voltage variation of 1mv for supply voltage range from 8 v to 18 v . due to novel curvature compensation , the circuit structure of the proposed reference is simple and both chip area and power consumption are small
Hspice仿真結(jié)果顯示：該基準源在- 40 100的溫度變化范圍內(nèi)，具有11ppm的低溫度系數(shù)；當電源電壓在8 18v變化時，輸出電壓變化量僅為1mv ；并且電路結(jié)構(gòu)簡單，具有較小的芯片面積和功耗。