- 邏輯設(shè)計(jì)
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logic design中文什么意思
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- Then , according to the requirement analysis , concept design , logic design and database design , the electronic instrument failure rate database was designed and the components failure rates and n factors in gjb / z299b - 98 were established in the database
其次，按照開發(fā)關(guān)系型數(shù)據(jù)庫(kù)所要求的需求分析、概念設(shè)計(jì)、邏輯設(shè)計(jì)和物理設(shè)計(jì)四個(gè)階段，設(shè)計(jì)了電子設(shè)備失效率數(shù)據(jù)庫(kù)并做了數(shù)據(jù)錄庫(kù)工作。 - According to the redundancy in digital circuits , we investigate the diversified redundancy - restraining techniques for lower - power cmos circuits . to erase the redundant transition of the clock , the logic design of double - edge - triggered flip - flop is presented and applied in sequential circuit design
為消除時(shí)鐘信號(hào)的兀余跳變，提出了利用時(shí)鐘兩個(gè)方向跳變的雙邊沿觸發(fā)器邏輯發(fā)計(jì)并應(yīng)用于時(shí)序電路設(shè)計(jì)中。 - On the one hand , we separate the system into four apartment , basic database , quoting for tenders , the document management and consumer information management , on the other hand , we are going on the logic design for the database in detail according to the requirment . we design the database ' s physical structure and distributing according to client end / server mode . we design the database equitment and the database with microsoft sql server
在應(yīng)用軟件開發(fā)上，按照客戶端服務(wù)器模式設(shè)計(jì)出數(shù)據(jù)庫(kù)的物理結(jié)構(gòu)及分布，在microsoftsqlserver上建立了數(shù)據(jù)庫(kù)設(shè)備及數(shù)據(jù)庫(kù)；在程序編碼上，采用面向?qū)ο蠛蜕芷诜ㄏ嘟Y(jié)合，開發(fā)出滿足功能設(shè)計(jì)的應(yīng)用軟件，并在用戶的應(yīng)用測(cè)試中不斷修改完善，同時(shí)給出相應(yīng)的技術(shù)文檔；在開發(fā)平臺(tái)的選擇上，主要用powerbuilder作為前端開發(fā)工具。 - Testing and debugging of logic design is also focused . the research work of this thesis mainly includes : ascertain needed function of net interface module according to the using environment , partition sub - modules of the system . define function of sub - modules and interface between them in detail
本論文的研究工作重點(diǎn)包括：根據(jù)網(wǎng)絡(luò)接口模塊的應(yīng)用環(huán)境，進(jìn)行系統(tǒng)需求分析，確定所需實(shí)現(xiàn)功能，而后進(jìn)行系統(tǒng)子模塊的劃分，明確各個(gè)子模塊功能、實(shí)現(xiàn)方法及其之間的接口。 - This thesis focuses on the ingress process module of ctu , which translates c - 5 dcp format to rainier 4gs3 . the specification analysis , architecture and logic design , functional simulation testbench design , synthesis report and testing result are discussed in this thesis . the research work mainly includes : the specification analysis and design requirements of ctu logic ; the architecture and logical design of ingress process module , which includes receive control fsm , send control fsm and cell position adjustment logic ; the performance improvement of ingress process module to receive and transmit data cell at the full line speed
本論文的主要研究工作包括：通信協(xié)議轉(zhuǎn)換邏輯的功能分析和設(shè)計(jì)需求；通信協(xié)議轉(zhuǎn)換邏輯上行方向的系統(tǒng)分析及體系結(jié)構(gòu)設(shè)計(jì)，包括上行接收狀態(tài)機(jī)、發(fā)送狀態(tài)機(jī)、信元內(nèi)字節(jié)位置調(diào)整機(jī)制等的設(shè)計(jì)；通信協(xié)議轉(zhuǎn)換邏輯上行方向的線速設(shè)計(jì)，主要是上行接收的線速設(shè)計(jì)，要使用流水設(shè)計(jì)技術(shù)；提出了高速實(shí)現(xiàn)roundrobin調(diào)度策略的實(shí)現(xiàn)方法，并設(shè)計(jì)實(shí)現(xiàn)了桶式移位器和優(yōu)先級(jí)編碼電路；應(yīng)用bfm仿真模型設(shè)計(jì)了上行處理各模塊的仿真testbench ，完成了各級(jí)模塊的模塊仿真和系統(tǒng)集成仿真。