例句與造句

1. The majority of the test vectors are used to check the connection of the pins of the device . those vectors for connection test can be removed from the vector base for the device under test when deltascan is applied together with boundary scan test . the total vectors are therefore eliminated
   測(cè)試矢量中大多數(shù)是用于測(cè)試引腳之間是否有短路或有引腳開(kāi)路情況的，引入deltascan測(cè)試ic的引腳的開(kāi)路和短路情況后，就可從xc5210 _ tq144的測(cè)試矢量集中去掉合并與短路，開(kāi)路測(cè)試有關(guān)的測(cè)試矢量，進(jìn)一步減少了邊界掃描所需的測(cè)試矢量。
2. This thesis discusses the realization of pcbs ict production through a concrete example in which boundary scan technology is applied , and presents a new method to improve the test speed , based on the analysis of boundary scan circuit and means for vector creation . he applys boundary scan ( bs ) to boundary - scan device on the board where bs features by easy vector creation , need less knowledge of the device
   本文結(jié)合一個(gè)具體電路板在線測(cè)試實(shí)現(xiàn)，首先討論了在ict中，采用邊界掃描元件測(cè)試技術(shù)實(shí)現(xiàn)在線測(cè)試生產(chǎn)；并在分析歸納各種測(cè)試方法的基礎(chǔ)上探索一種新的改進(jìn)方法，即將deltascan技術(shù)與邊界掃描技術(shù)相結(jié)合以減少測(cè)試矢量，增加測(cè)試速度的一種實(shí)用方法。
3. And more than 70 % hardware are tested during microcode self - test since the execution of micro program can cover other data paths . boundary scan is designed according to ieee1149 . 1 , and some other instructions such as degug , runbist are provided to support internal fault testing , online debugging and built - in self - test besides the several necessary insructions . internal scan is implemented by partial scan , through this the boundary of logic component and user - cared system registers can be selected to be scanned
   Bist用于測(cè)試cpu的微碼rom ,其它ram則利用微碼rom中的微程序進(jìn)行測(cè)試,而微程序的運(yùn)行則可以順帶覆蓋其它數(shù)據(jù)通路,從而使高達(dá)70 %的硬件得到測(cè)試;邊界掃描按ieee1149 . 1標(biāo)準(zhǔn)設(shè)計(jì),除必備的幾條邊界掃描指令外,還提供了debug 、 runbist等指令以支持內(nèi)部故障測(cè)試、在線調(diào)試及內(nèi)建自測(cè)試;內(nèi)部掃描采用部分掃描策略,選擇邏輯部件的邊界及用戶關(guān)心的系統(tǒng)寄存器進(jìn)行掃描,從而實(shí)現(xiàn)了硬件邏輯劃分,方便了后續(xù)的測(cè)試碼產(chǎn)生和故障模擬,并為在線調(diào)試打下了基礎(chǔ)。
4. Finally the design of rs decoder in this chip is described as an example of the hardware / software co - design based on asip , the construction and application of asip is also analyzed . the fourth chapter introduces the design flow using eda tools based on standard cell , then it presents the dft of this chip in detail which uses following techniques : full scan , bist and boundary scan to improve the fault coverage
   第四章，在對(duì)本芯片的基于標(biāo)準(zhǔn)單元eda設(shè)計(jì)流程進(jìn)行了簡(jiǎn)要說(shuō)明基礎(chǔ)上，對(duì)本芯片采用的可測(cè)試性設(shè)計(jì)進(jìn)行了詳細(xì)的分析和說(shuō)明，本芯片中有機(jī)結(jié)合了多種可測(cè)試性設(shè)計(jì)技術(shù)：基于全掃描的方式、 bist測(cè)試技術(shù)、邊界掃描技術(shù)，保證了很高的測(cè)試故障覆蓋率。
5. The main contents are as follows : the structure of mixed - signal circuit which newly - defined in ieee1149 . 4 std is analyzed in detail , especially anolog boundary module and test bus interface circuit . on the basis of mixed - signal boundary scan technology , a scheme of mixed - signal boundary - scan test system is presented and the hardwares are implemented , including the controller and display unit
   主要研究的內(nèi)容以及所作的工作如下:詳細(xì)分析了ieee1149 . 4標(biāo)準(zhǔn)中針對(duì)混合信號(hào)電路測(cè)試新增的結(jié)構(gòu),即模擬邊界模塊及測(cè)試接口電路?；诨旌闲盘?hào)邊界掃描技術(shù)標(biāo)準(zhǔn),提出混合信號(hào)邊界掃描控制器的設(shè)計(jì)方案并實(shí)現(xiàn)了其硬件設(shè)計(jì),包括邊界掃描控制模塊、顯示驅(qū)動(dòng)模塊等。
6. It's difficult to find boundary scan in a sentence. 用boundary scan造句挺難的
7. Then a comparison is made according to their characters and the application scope of each method is determinate . from that we get the whole scheme of design for testability of dspc50 , which is using boundary scan to improve the board - level testability of the chip and using full - scan in designing the nuclear circuit to reduce the difficulty of testing the chip
   在此基礎(chǔ)上得到dspc50的可測(cè)性設(shè)計(jì)的整體方案，即采用邊緣掃描設(shè)計(jì)提高芯片在板級(jí)的可測(cè)性，同時(shí)用全掃描思想設(shè)計(jì)芯片核心電路，以降低芯片本身測(cè)試的難度，即將芯片的全掃描設(shè)計(jì)包含入邊緣掃描系統(tǒng)。
8. From the view point of the foundation of dft ( which includes the testable measure of gate - level circuits , the testable and controllable measure of functional - level , the flow and methodology of dft and so on ) , the author introduce some common testing technology such as scan and bist in modern times . especially the boundary scan technology has been widely adopted in the dft of vlsi . with the special controller , the testing vector could be scanned to the corresponding ports of inner cores from the testing input ports , and the response could also be shifted to the testing output ports
   本文從可測(cè)性設(shè)計(jì)的基礎(chǔ)理論出發(fā)（包括門級(jí)電路的可測(cè)性測(cè)度、功能級(jí)上的可測(cè)性和可控性、可測(cè)性設(shè)計(jì)的流程和方法等） ，介紹了現(xiàn)代常用的可測(cè)性技術(shù)，比如：掃描技術(shù)、內(nèi)嵌自測(cè)試技術(shù)等，特別是邊緣掃描技術(shù)已經(jīng)廣泛地應(yīng)用到vlsi的可測(cè)性設(shè)計(jì)之中，它通過(guò)特定的控制器，從相應(yīng)的測(cè)試輸入端口將測(cè)試向量掃描至芯核所對(duì)應(yīng)的管腳，再將結(jié)果從相應(yīng)的測(cè)試輸出端口掃出。
9. In the logic design , the fundamentals and characteristics of ieee std . 1149 . 1 specification and usb protocol are introduced first of all . according to altera ’ s fpga cyclone , it analyzes the architecture and jtag instructions of boundary scan test ( bst ) . then the dissertation analyzes how to program cyclone device and offer the scheme of the design which is realized in verilog hdl by modelsim and quartus ii software
   在接口邏輯設(shè)計(jì)中,首先分析ieee1149 . 1標(biāo)準(zhǔn)和usb協(xié)議,理解邊界掃描測(cè)試和usb數(shù)據(jù)傳輸?shù)墓ぷ鞣绞?然后針對(duì)altera公司的fpga器件cyclone ,通過(guò)分析它的邊界掃描測(cè)試結(jié)構(gòu)和各種jtag指令,研究它的編程過(guò)程和編程特點(diǎn),并提出設(shè)計(jì)方案。
10. In this thesis , the boundary scan technique is discussed in detail and a boundary - scan test system based on computer is also developed . the main contents can be summarized as follows : 1 . the ieee std 1149 . 1 boundary scan testing standard is researched , and the mathematical description model and some basic theorems of boundary scan testing process is analyzed subsequently
    論文的研究?jī)?nèi)容及主要工作包括: 1 、對(duì)邊界掃描技術(shù)的基本理論和方法進(jìn)行了分析和研究,并對(duì)邊界掃描測(cè)試過(guò)程中的數(shù)學(xué)描述模型以及邊界掃描測(cè)試的基本定理進(jìn)行總結(jié),為邊界掃描測(cè)試生成算法的研究以及邊界掃描測(cè)試系統(tǒng)的開(kāi)發(fā)奠定基礎(chǔ)。
11. So here introduces a new method - the combination of boundary scan with deltascan , in which deltascan is applied to do short and open test in ict , so that the number of vectors used to test circuit short and open in boundary can be eliminated . all vector test , including boundary scan test , need to create test vectors
    任何邏輯元件的矢量測(cè)試，包括邊界掃描測(cè)試，都必須先生成測(cè)試矢量，然后用這些測(cè)試矢量作為輸入端的激勵(lì)信號(hào)，因此測(cè)試矢量是矢量測(cè)試的基礎(chǔ)，測(cè)試矢量生成方法的難易程度和測(cè)試矢量數(shù)目是邊界掃描技術(shù)能否在實(shí)際中應(yīng)用的關(guān)鍵。
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