例句與用法

1. Cryptogrammic chip introduced in this paper has been tested on the altera ' s apex20ke fpga . the main clock frequency reached 40mhz . the chip includes 30 , 000 les . in order to utilize esb resource in altera ' s chip , we adopted embedded rom and ram and can realize the function of whole system with only one chip . lt is the embodiment of methodology and notion of sopc ( system on a programmable chip ) . the simulation of this cryptogrammic chip proves the correctness of function of the chip , which shows that the important ideology based reconfigurable architecture has special significance in designing of cryptogrammic chip
   本文所闡述的密碼芯片在altera公司的apex20kefpga上進(jìn)行了測(cè)試。工作頻率達(dá)到了40mhz ，占用了3萬(wàn)個(gè)le . ，利用altera器件的esb資源，采用內(nèi)置ram和內(nèi)置rom設(shè)計(jì)方法，用一片芯片即可實(shí)現(xiàn)整個(gè)系統(tǒng)的功能，充分體現(xiàn)了sopc的設(shè)計(jì)方法和理念，對(duì)芯片的仿真和測(cè)試均證明芯片功能正確，表明基于可重組體系結(jié)構(gòu)這一重要思想在密碼芯片設(shè)計(jì)中具有特殊的意義。該芯片的設(shè)計(jì)遵循h(huán)dl設(shè)計(jì)方法學(xué)的一般方法。
2. The design of this chip sticks to the general methodology of hdl design . lt is entered in hdl format with innoveda ' s visual hdl and simulated with modelsim simulator , after synthesized with fpga compiler ii , the edif is entered in quartus ii , which is supplied by altera corporation to place and route . the sdo file produced by quartus ii is backannotated to the netlists and timing - simulation is been done . the success of this cryptogrammic chip also shows the effectiveness and advantage of the methodology of high level design with hdl
   在innoveda的visualhdl設(shè)計(jì)平臺(tái)上用hdl語(yǔ)言完成了設(shè)計(jì)輸入，使用modelsim仿真器完成了功能仿真，使用synopsys的fpgacompiler進(jìn)行了基于alterafpga庫(kù)的網(wǎng)表綜合，最后將edif網(wǎng)表輸入altera的布局布線工具quartus中進(jìn)行了布局布線，將生成的sdo文件反標(biāo)到modelsim仿真器中進(jìn)行了時(shí)序仿真，該設(shè)計(jì)的成功，再一次表明了hdl設(shè)計(jì)方法的正確性和有效性。
3. This paper systematically presents the whole design process of a cryptogrammic chip based on reconfigurable architecture . firstly it begins with a brief introduction to the background of the cryptogrammic chip design , and it clearly states the characteristic and the researching thoughts of cryptogrammic chip design with hdl . then the design environment and cipher algorithms are introduced briefly
   本文系統(tǒng)地論述了基于可重組體系結(jié)構(gòu)的密碼芯片設(shè)計(jì)的全過(guò)程，文章首先闡述了該設(shè)計(jì)的課題背景，給出了使用hdl方法設(shè)計(jì)密碼芯片的特點(diǎn)和研究思路，然后對(duì)芯片的設(shè)計(jì)環(huán)境作了簡(jiǎn)要說(shuō)明，并對(duì)密碼算法進(jìn)行了簡(jiǎn)單介紹。