例句與用法

1. to decrease the area of the chip, resource sharing, which is a synthesized optimized method of eda tools, was used in the project . the code was verified in fpga soft ware environment . synthesized netlists based on fpga and asic were given in the paper for future work
   本課題所設計的微處理器的整數(shù)單元和浮點單元均采用硬件描述語言vhdl進行建模，為降低芯片面積，將資源共享這一eda工具的綜合優(yōu)化方法應用于設計中，并在現(xiàn)有條件下進行了簡單的fpga驗證，考慮到今后的asic設計，本文給出了基于fpga和基于asic的兩種綜合網表。
2. the design of this chip sticks to the general methodology of hdl design . lt is entered in hdl format with innoveda's visual hdl and simulated with modelsim simulator, after synthesized with fpga compiler ii, the edif is entered in quartus ii, which is supplied by altera corporation to place and route . the sdo file produced by quartus ii is backannotated to the netlists and timing-simulation is been done . the success of this cryptogrammic chip also shows the effectiveness and advantage of the methodology of high level design with hdl
   在innoveda的visualhdl設計平臺上用hdl語言完成了設計輸入，使用modelsim仿真器完成了功能仿真，使用synopsys的fpgacompiler進行了基于alterafpga庫的網表綜合，最后將edif網表輸入altera的布局布線工具quartus中進行了布局布線，將生成的sdo文件反標到modelsim仿真器中進行了時序仿真，該設計的成功，再一次表明了hdl設計方法的正確性和有效性。