board-level造句
例句與造句
- Board - level design for testability based on jtag
的板級可測試性設計 - Application of boundary scan technique to the design for board - level test
邊界掃描技術在板級可測性設計中的應用 - To that end , a demonstrable board - level commitment to an effective formal quality management system must exist
為此，公司高層必須為一個有效正式的質量管理體系提供可以證明的承諾。 - Using visual c + + , a board - level test vector generation and fault diagnoses software were designed and carried out
在visualc + +環(huán)境下,設計并實現(xiàn)了板級測試矢量生成軟件和故障診斷軟件。 - The results show that the viscoelasticity of pcb and its size have distinct influence on dynamic properties of pcb under board - level drop impact
結果表明，電路板的黏性系數(shù)和尺寸對板的動力學特性有顯著影響。 - It's difficult to find board-level in a sentence. 用board-level造句挺難的
- Otherwise , by using some board - level test theories and methods , a test resolution , including bst infrastructure integrity test , interconnect test and cluster test was given
另外,結合板級測試的相關理論和方法,提出了一套板級測試解決方案,包括掃描鏈完整性測試、互連測試和簇測試。 - He holds a post - graduate degree in business computing , besides having board - level experience in corporate communications , bid management , business development , corporate finance , and information technology
他擁有商業(yè)計算機專業(yè)的碩士學位，同時在企業(yè)通訊、招標管理、業(yè)務發(fā)展、公司融資、信息科技等行業(yè)均擔任過董事職位。 - Indeed , most directors are unaware of the growing body of knowledge that is now available about the work of directors , board - level effectiveness and the exercise of power of the modern corporate entity - what is now called corporate governance
事實上，大部分董事都不知道現(xiàn)時有一門發(fā)展迅速、稱為公司管治的學科。這門學科專門研究有關董事職務、董事局的工作效率、現(xiàn)代化公司組織的權力運用等。 - Followed above , this dissertation has much content about the hardware design which include dsp , fpga , ddr sdram memory bank interface circuit , pci , power circuit , board - level interconnection design . this part puts much emphasis on key circuits many of which require us to have deeply known the components adopted and involved specifications
這部分主要是對電原理圖的重要地方和需要注意的地方進行重點闡述,包括dsp 、 fpga 、 ddrsdram內(nèi)存條接口電路、 pci接口電路、電源、板級互連等部分。 - Then a comparison is made according to their characters and the application scope of each method is determinate . from that we get the whole scheme of design for testability of dspc50 , which is using boundary scan to improve the board - level testability of the chip and using full - scan in designing the nuclear circuit to reduce the difficulty of testing the chip
在此基礎上得到dspc50的可測性設計的整體方案，即采用邊緣掃描設計提高芯片在板級的可測性，同時用全掃描思想設計芯片核心電路，以降低芯片本身測試的難度，即將芯片的全掃描設計包含入邊緣掃描系統(tǒng)。 - Further more , by means of analyzing bios technology , the dissertation expounds the board - level initialization process and key technologies of embedded system . to study the basic principle of bootloader , it gives a detailed statement of gurb based on the source code , and put forward the structure and designing ideas of bootloader in embedded system
通過分析pc機的bios技術闡述了嵌入式系統(tǒng)中板級初始化流程和技術重點,并從源代碼分析入手詳細分析了pc機gurb引導程序設計技術,提出了嵌入式系統(tǒng)上bootloader的程序結構和設計思想。 - It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ) , 5 - stage pipeline , hardware multiplier and divider , interrupt controller , 16 - bit i / o port and a flexible memory controller . new modules can easily be added using the on - chip amba ahb / apb buses . it has flexible peripheral interfaces , so can be used as an independent processor in the board - level application or as a core in the asic design
它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：采用分離的指令和數(shù)據(jù)cache （哈佛結構） ，五級流水，硬件乘法器和除法器，中斷控制器， 16位的i / o端口和靈活的內(nèi)存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。