例句與造句

1. Techniques for optimizing the cascode transistor are proposed
   我們給出了對(duì)cascode場(chǎng)效應(yīng)管的優(yōu)化方法。
2. Cascode transistor circuit
   串聯(lián)晶體管電路
3. For the demand of output swing , the bias is provided by high - swing cascode current mirrors
   為了獲得高輸出擺幅,設(shè)計(jì)低壓共源共柵電流鏡為運(yùn)放提供偏置。
4. The impact of the cascode transistor on the noise and linearity performance of the cmos lna is discussed in detail
   本文詳細(xì)分析了cascode場(chǎng)效應(yīng)管對(duì)cmos低噪聲放大器的噪聲和線性性能的影響。
5. By taking the capacitance into consideration , we show new noise figure optimization methods for cmos cascode lnas
   在考慮了該電容以后，本文給出了新的cmoscascode結(jié)構(gòu)低噪聲放大器的優(yōu)化方法。
6. It's difficult to find cascode in a sentence. 用cascode造句挺難的
7. Based on the volterra series , expressions describing the third - order intermodulation distortion in cmos cascode lnas are derived
   基于伏特拉級(jí)數(shù)，本文推導(dǎo)出了描述cmoscascode結(jié)構(gòu)低噪聲放大器三階互調(diào)指標(biāo)的方程。
8. In this paper , the traditional cascode structure of cmos lna is considered as a two - stage amplifier and inter - stage matching network is introduced accordingly
   本文也對(duì)cmos低噪聲放大器進(jìn)行了分析，將傳統(tǒng)共源共柵結(jié)構(gòu)看作二級(jí)放大器級(jí)聯(lián)形式，并由此引入級(jí)間匹配網(wǎng)絡(luò)。
9. Based on the study of circuit cells which are applied in sige bicmos operational amplifier , the telescope cascode configuration is selected to realize high speed and high gain
   其次,通過(guò)對(duì)sigebicmos運(yùn)算放大器中電路單元的研究,并結(jié)合運(yùn)放實(shí)際設(shè)計(jì)指標(biāo),選擇套筒式共源共柵結(jié)構(gòu)作為運(yùn)放的主體結(jié)構(gòu)以確保高速、高增益的實(shí)現(xiàn)。
10. 2 . the input stages of the ccii and the operational amplifier in transimpedance implifier are realized with folded cascode amplifier to reach high cmrr , large open loop gain and low offset
    2 .為了提高儀表放大器的電源抑制比,并得到大的開(kāi)環(huán)增益,相對(duì)低的失調(diào)等性能,電流傳輸器的輸入級(jí)和跨阻放大器中運(yùn)算放大器輸入級(jí)均采用折疊共源共柵放大器。
11. According to the analysis of the whole communication system , we verified the feasibility of the design goal put forward previously and used a topology of cascode with source degeneration to design a differential lna
    通過(guò)對(duì)衛(wèi)星通信系統(tǒng)的鏈路分析,根據(jù)實(shí)際系統(tǒng)需要,確定了低噪放模塊的設(shè)計(jì)指標(biāo)。采用常用的共源共柵拓?fù)浣Y(jié)構(gòu),設(shè)計(jì)了一個(gè)差分結(jié)構(gòu)的lna 。
12. The lna with source inductor degeneration is analyzed in detail , which is used most widely in current . base on the analysis , a cascode structure is presented to minimize the effect of gate - drain capacitance cgd
    針對(duì)目前l(fā)na中應(yīng)用最廣泛的源極電感負(fù)反饋結(jié)構(gòu),進(jìn)行了詳細(xì)分析,在此基礎(chǔ)上對(duì)該結(jié)構(gòu)做出了優(yōu)化,采用共源共柵級(jí)聯(lián)結(jié)構(gòu),減小了柵漏電容cgd的影響。
13. The drive stage is made up of cascode class - f topology . a “ big ” mosfet is used in the class - e output stage . the thesis did the simulation of the pa by ads with the tsmc 0 . 18 m rf cmos model , and completed the layout of the pa
    本文設(shè)計(jì)了一種新穎的射頻cmos功率放大器,采用兩級(jí)差分結(jié)構(gòu),用f類共源共柵結(jié)構(gòu)作為驅(qū)動(dòng)級(jí),輸出級(jí)采用大尺寸mos管的e類功率放大器。
14. The full noise and linearity analysis of the low noise amplifier ( lna ) constructed by cascode structure with source degeneration and the optimization methods of the two mosfets in this structure according to the noise and linearity performance
    I對(duì)共源共柵矚ascode ）源極去耦舊ourcedegeneration ）結(jié)構(gòu)低噪放做了完整的噪聲和線性分析，得到該結(jié)構(gòu)中兩個(gè)mosfet針對(duì)噪聲性能和線性性能的優(yōu)化方法。
15. The main research content about this two subcircuits are as follows : 1 . the precision and dynamic range of several typical current mirrors are discussed and an active input regulated - cascode output current mirror is adopted as the current duplicate circuits in ccii
    在這兩個(gè)子電路中主要進(jìn)行了如下研究: 1 .研究了幾種常用的電流鏡的電流傳輸精度和動(dòng)態(tài)范圍,并最終選擇有源輸入校準(zhǔn)型電流鏡作為電流傳輸器中的電流傳輸電路。
16. On the one hand , the design uses low voltage cascode op framework to improve its gain ; on the other hand , it applies self - bias and cascode structure to the whole sensing circuit . by using the improved method , we have successfully obtained low power consumption , low offset , high linear and high psrr ptat current generator under low power supply
    在電路設(shè)計(jì)上一方面改進(jìn)運(yùn)放結(jié)構(gòu),采用低壓共源共柵結(jié)構(gòu)以提高其增益,另一方面整體傳感電路采用自偏置結(jié)構(gòu)和共源共柵電流鏡結(jié)構(gòu),在低電源電壓下成功設(shè)計(jì)了低功耗、低失調(diào)、高線性度和高電源電壓抑制比的ptat電流產(chǎn)生電路。
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