edge-trigger造句
例句與造句
- Design of double - edge - triggered dynamic flip - flop and its application
雙邊沿動(dòng)態(tài)觸發(fā)器的設(shè)計(jì)及其應(yīng)用 - A det ( double - edge - triggered ) shift counter designed with the det shift register is demonstrated
使用該移位寄存器設(shè)計(jì)雙邊沿移位計(jì)數(shù)器的實(shí)例被演示。 - Semiconductor integrated cicuits . detail specification for type jt54f74 fttl dual d positive edge - triggered flip - flops
半導(dǎo)體集成電路. jt54f74型fttl雙上升沿d觸發(fā)器詳細(xì)規(guī)范 - To eliminate the bootless power dissipation of the redundant transition of the clock , a design method named det ( double - edge - triggered ) shift register is proposed
摘要從消除時(shí)鐘信號(hào)冗馀跳變而致的無效功耗的要求出發(fā)，提出雙邊沿移位寄存器的設(shè)計(jì)思想。 - Then , we propose a design method named det ( double - edge - triggered ) shift register to eliminate the bootless power dissipation of the redundant transition of the clock
接著，從消除時(shí)鐘信號(hào)冗余跳變而致的無效功耗的要求出發(fā)，提出雙邊沿移位寄存器的設(shè)計(jì)思想。 - It's difficult to find edge-trigger in a sentence. 用edge-trigger造句挺難的
- According to the redundancy in digital circuits , we investigate the diversified redundancy - restraining techniques for lower - power cmos circuits . to erase the redundant transition of the clock , the logic design of double - edge - triggered flip - flop is presented and applied in sequential circuit design
為消除時(shí)鐘信號(hào)的兀余跳變，提出了利用時(shí)鐘兩個(gè)方向跳變的雙邊沿觸發(fā)器邏輯發(fā)計(jì)并應(yīng)用于時(shí)序電路設(shè)計(jì)中。 - From the concept of triditional master - slave flip - flop , we propose a simplified positive edge - triggered flip - flop and prove the traditional positive edge - triggered flip - flop is the master - slave flip - flop designed based on basic flip - flop with single - rail input
并且從傳統(tǒng)主從結(jié)構(gòu)觸發(fā)器出發(fā)，提出了簡化結(jié)構(gòu)的維持阻塞型觸發(fā)器設(shè)計(jì)。針對(duì)數(shù)字電路中大量存在的冗余現(xiàn)象，本文討論了冗余抑制原理以及相應(yīng)的冗余抑制技術(shù)。 - Based on the construction of traditional flip - flop , we propose a novel edge - triggered flip - flip using one latch controlled by narrow pulse according to race - hazard of clock . then this principle is adopted in ternary circuit , a new ternary d type edge - triggered flip - fiop based on cmos transmission gate is proposed
在二值單閂鎖結(jié)構(gòu)邊沿觸發(fā)器的基礎(chǔ)上，把利用時(shí)鐘信號(hào)競爭冒險(xiǎn)的思想應(yīng)用于三值電路中，提出了基于cmos傳輸門的二值d型時(shí)鐘信號(hào)競爭型邊沿觸發(fā)器。