netlist造句
例句與造句
- Furthermore , timing simulation and static - state timing analysis were made . by doing these , netlist files were got
并進(jìn)一步做時(shí)序仿真和靜態(tài)時(shí)序分析,產(chǎn)生輸出網(wǎng)表文件,最后下載到fpga進(jìn)行系統(tǒng)實(shí)現(xiàn)。 - The effects of the time sequence netlist simulation of the circuit and fpga verification indicate the correctness of the circuit design
行為仿真結(jié)果、綜合布線后的門級(jí)仿真結(jié)果以及fpga驗(yàn)證結(jié)果均表明了設(shè)計(jì)的正確性。 - This tool could analyze the connection relationship between the submodels of the system designed with simulink and give out a verilog hdl description of the netlist
它可以對(duì)simulink中頂層的各個(gè)模塊之間的連接關(guān)系進(jìn)行分析,并將分析的結(jié)果用veriloghdl描述出來(lái)。 - At last , eda tools generate netlist for semiconductor manufactory . the eda technology and veriolog hdl must speed up the design of risc cpu in china
高性能精簡(jiǎn)指令集微處理器的設(shè)計(jì)通過(guò)運(yùn)用veriloghdl語(yǔ)言， eda工具，和asic設(shè)計(jì)的主要流程，縮短了設(shè)計(jì)周期，加快其產(chǎn)品的面市速度。 - According to the hardware structure of the main experiment board , the circuit netlist transformation program translates the visual circuit description to the actual netlist
根據(jù)實(shí)驗(yàn)主板的硬件結(jié)構(gòu)，設(shè)計(jì)的專用電路網(wǎng)表轉(zhuǎn)化程序，將便于用戶理解的圖形化的電路描述轉(zhuǎn)化為便于實(shí)際硬件操作的電路網(wǎng)表。 - It's difficult to find netlist in a sentence. 用netlist造句挺難的
- It induces logic and delay to waveform , and describes the continuous states of nodes in netlist by waveform . it can realize simulating continuous states for integrated circuits by computing waveforms
它把邏輯和延遲有機(jī)地結(jié)合起來(lái)歸納為波形，并用波形來(lái)描述電路網(wǎng)表中節(jié)點(diǎn)的連續(xù)時(shí)間狀態(tài)，通過(guò)對(duì)波形的計(jì)算實(shí)現(xiàn)整個(gè)電路的連續(xù)時(shí)間狀態(tài)模擬。 - Simulation of digital circuits is based on computing of logic and delay for component in circuit netlist , so for obtaining correct simulation result , i must have logic computing correctly and delay analysis accuracily
由于數(shù)字電路的模擬是基于對(duì)電路網(wǎng)表中的元件進(jìn)行邏輯和延時(shí)計(jì)算的，所以要想得到正確的模擬結(jié)果，必須進(jìn)行正確的邏輯運(yùn)算和準(zhǔn)確的延時(shí)分析。 - Recurring to the circuit netlist , the mcu of the main board finishes the digital setting for the parameters and the structure of the experiment circuit , which realize to do all kinds of electronics experiments in the same main experiment board
控制實(shí)驗(yàn)主板的單片機(jī)借助于電路網(wǎng)表所提供的信息，完成實(shí)驗(yàn)電路結(jié)構(gòu)和參數(shù)的全數(shù)字化設(shè)置，從而實(shí)現(xiàn)了在同一實(shí)驗(yàn)主板上完成不同的電工電子實(shí)驗(yàn)。 - Then describes the 4 function modules in vhdl , the vhdl programs have passed compile and debug in maxplus ii , the results of function simulation and timing simulation all prove that the design is correct , at last , maxplus ii generates a netlist file which can be download into chip
然后使用vhdl硬件描述語(yǔ)言對(duì)四大功能模塊進(jìn)行描述，在maxplus環(huán)境下編譯、調(diào)試通過(guò)，功能仿真和時(shí)序仿真結(jié)果證明設(shè)計(jì)正確，最后生成可下載的網(wǎng)表文件。 - It presents the verification strategy used in the whole eda design flow of the chip . the simulation on module level ( inc . post - layout ) uses the software event - driven simulator , the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator , for the gate - level netlist produced by using top - down design flow , the sta tool can analyze the static timing , and more formal verification is used to ensure the correct function
本章還提出了系統(tǒng)在整個(gè)eda設(shè)計(jì)流程中的設(shè)計(jì)驗(yàn)證策略方法：模塊級(jí)的模擬(包括布線后的模擬)全部采用事件驅(qū)動(dòng)式的軟件模擬工具來(lái)驗(yàn)證，各大模塊的聯(lián)合模擬及整個(gè)芯片的功能驗(yàn)證(寄存器傳輸級(jí)與門級(jí))使用基于周期的模擬工具和硬件仿真器；對(duì)于采用top - down的設(shè)計(jì)方法得到的門級(jí)網(wǎng)表使用專門的靜態(tài)時(shí)序分析工具來(lái)進(jìn)行時(shí)序分析以及采用形式驗(yàn)證來(lái)保證正確的功能。 - For above problems , i design boole process - based algorithm . for example , hazards finding theory work out a formal method of finding hazards by waveforms computing ; waveforms increasing algorithm settle the defect of boole process in feedback cycle treatment ; false paths discerning algorithm can delete useless nodes in netlist effectively ; inertia conflict eliminating method describes the state of nodes truelier and reduces computing
其中，冒險(xiǎn)檢測(cè)定理給出了通過(guò)波形運(yùn)算檢測(cè)電路中冒險(xiǎn)現(xiàn)象的哈爾濱工程大學(xué)碩士學(xué)位論文形式化方法;波形遞增算法解決了boole過(guò)程在處理電路中反饋環(huán)問(wèn)題上的缺陷;偽路徑識(shí)別算法能夠有效地去除電路網(wǎng)表中的無(wú)用節(jié)點(diǎn);而慣性沖突消除法能使對(duì)節(jié)點(diǎn)狀態(tài)的描述更加真實(shí)，并減少了計(jì)算量。 - The main work includes the deep study of microprocessor theory , the system - level design of the soft core that is performed based on it , the system function definition and partition , the design of all the functional modules . after completing system - level and algorithm - level designs , the rtl implementations of each module are performed and the functional simulation and fpga verification are carried out on the rtl codes . at last , the rtl codes are synthesized with synopsys " design compiler and the gat - level netlist is gotten
具體工作包括對(duì)微處理器理論的深入研究，并在此基礎(chǔ)上完成16位risc微處理器軟核16rmpu的系統(tǒng)級(jí)設(shè)計(jì)，實(shí)現(xiàn)系統(tǒng)功能定義和系統(tǒng)劃分；完成軟核各個(gè)模塊的算法級(jí)設(shè)計(jì)和rtl級(jí)設(shè)計(jì)，并對(duì)軟核的rtl級(jí)代碼進(jìn)行仿真和fpga驗(yàn)證；對(duì)軟核進(jìn)行dc ( designcompiler )綜合，生成后端布局布線所需要的網(wǎng)表文件，最終實(shí)現(xiàn)微處理器軟核的設(shè)計(jì)。