例句與造句

1. The application of quartus 4 . 1 in the comprehensive experiment teaching
   1在綜合性實(shí)踐教學(xué)中的應(yīng)用
2. At last , the system is synthesized and placed and layout by quartus ii , and uses fpga to implement the design
   最后，文章給出了整個(gè)設(shè)備控制器系統(tǒng)的編譯結(jié)果，并用fpga器件測(cè)試驗(yàn)證。
3. Use different eda tools , including modelsim , synplify , quartus , etc . at different stages of what has been designed
   在設(shè)計(jì)的不同階段使用了不同的eda工具，包括modelsim 、 synplify 、 quartus等等。
4. After these , the usb host controller was simulated , synthesized and placed and layout by activehdl , synplify and quartus ii
   并分別以activehdl 、 synplify ，和quartus完成了usb主控制器的前后仿真、綜合與布局布線。
5. At last , the simulation and test are introduced in the eda software of max + plus and quartus . the result and discussion are also given
   最后分別在max + plus和quartus兩個(gè)集成開發(fā)環(huán)境下對(duì)設(shè)計(jì)進(jìn)行仿真驗(yàn)證和分析討論。
6. It's difficult to find quartus in a sentence. 用quartus造句挺難的
7. This jpeg coding system is designed and simulated by quantursii software which is the fpga design tool of altera company . hole design need nearly 12600 lcs of cyclone device
   本設(shè)計(jì)采用altera公司的quartus軟件設(shè)計(jì)和仿真，采用cyclone系列器件需要約12600個(gè)lc 。
8. Finally , we using some software and hardware , such as matlab quartus ii and logic analysis system , to realize the whole circuit function by fpga
   通過matlab仿真，利用altera公司開發(fā)的quartus設(shè)計(jì)、編譯、仿真軟件平臺(tái)，采用相關(guān)硬件測(cè)試手段，最終完成電路的fpga實(shí)現(xiàn)和調(diào)試。
9. To validate the correctness of each module , author use quartus and modelsim software to implement software simulation , designed the pcb board based on fpga chip and finished circuit debug
   為驗(yàn)證模塊的正確性,不但通過quartus和modelsim進(jìn)行軟件仿真,還設(shè)計(jì)制作了基于fpga的pcb板,并完成了電路調(diào)試。
10. The circuit is synthesized by synplify pro which is synplicity ' s synthesis tool and emulated by quartus ii which is altera ' s developing tool , which has proved the feasibility and correctness of the circuit
    采用硬件描述語(yǔ)言vetilog編寫了硬件電路程序，并使用synplicity的綜合工具synplifypro和altera開發(fā)工具quartus對(duì)電路系統(tǒng)進(jìn)行了綜合與仿真驗(yàn)證，證明了硬件電路的可行性與正確性。
11. Then this paper introduces a quick and effective flow to translate the design structure of asic to that of fpga as well as some related eda tools like quartus ii , certify , synplify pro and amplify physical optimizer
    通過對(duì)asic設(shè)計(jì)流程的研究，論文提出一種快速、高效的將asic設(shè)計(jì)轉(zhuǎn)化為fpga設(shè)計(jì)的流程，并且介紹實(shí)現(xiàn)此流程的相關(guān)eda工具( quartus ， certify ， synplifypro ， amplifyphysicaloptimizer ) 。
12. Simulations are executed in altera ’ s quartus ii environment with altera ’ s stratix family fpgas using verilog hdl after analysis . the results show that the sfn adapter can properly insert mip into transport stream and the time to be delayed in sync system can be correctly calculated and carried out with fifo
    在對(duì)每一個(gè)模塊的設(shè)計(jì)要點(diǎn)做了詳細(xì)說明之后,采用verilog語(yǔ)言編寫各模塊邏輯代碼,在altera公司的quartusii5 . 0集成開發(fā)環(huán)境下,基于altera公司stratix系列fpga對(duì)各模塊及整個(gè)單頻網(wǎng)適配器進(jìn)行了仿真。
13. It is the first time that driving chip used by pdp is applied to the fed panel . by adopting the new ic and the novel driving method , the developed grey scale modulator achieve high flexbility , stability and high integration . the circuit system includes cyclonetm fpga from altera and stv7610 from st microelectronic . with the capability of generating two kinds of modulating waveform , it has the advantages of flexible configuration , high display - quality , high integration and low cost . fpga design is based on the quartus platform . data transforming and the system controlling are achieved by using single fpga
    基于altera公司cyclone系列fpga和st公司stv7610驅(qū)動(dòng)芯片設(shè)計(jì)的fed顯示器的灰度調(diào)制電路系統(tǒng)可以支持兩種調(diào)制波形,具有配置靈活,顯示性能好等優(yōu)點(diǎn),其集成度為原有系統(tǒng)的三倍,且造價(jià)更低廉;基于quartusii軟件平臺(tái)進(jìn)行了fpga的系統(tǒng)開發(fā)與優(yōu)化,采用單片fpga完成了全部的數(shù)據(jù)轉(zhuǎn)換和系統(tǒng)控制功能, fpga的可編程特性使系統(tǒng)的設(shè)計(jì)具有充分的靈活性和可擴(kuò)展性。
14. The logic design of interface circuit is realized in verilog hardware description language ( hdl ) . function simulation is finished by modelsim software . after the synthesis , placing , routing and obtaining delay information by develop tool quartus ii4 . 0 , timing simulation is accomplished by modelsim software
    接口電路的邏輯設(shè)計(jì)采用硬件描述語(yǔ)言veriloghdl ,先借助modelsim軟件進(jìn)行功能仿真驗(yàn)證,在quartusii4 . 0的集成開發(fā)環(huán)境中完成綜合、布局布線并提取元器件和網(wǎng)線上的實(shí)際延遲信息后,再借助modelsim軟件進(jìn)行時(shí)序仿真驗(yàn)證。
15. At last the algorithm of ddmf is achieved by the investigation tool of altera company ? quartus ii and the vhdl language , and its ip core is also achieved which is used not only in the satellite navigation position system , but also in the long pn code dsss system . ddmf investigated in the dissertation gives a good way to design the rapid pn code acquisition in the beidou project , and the technology has the definite theory and practice significance
    此外還應(yīng)用altera公司的最新的fpga開發(fā)工具quartusiiv5 . 1 ,采用了國(guó)際標(biāo)準(zhǔn)的硬件描述語(yǔ)言? vhdl語(yǔ)言,對(duì)數(shù)字差動(dòng)匹配濾波器和傳統(tǒng)匹配濾波器算法予以實(shí)現(xiàn),開發(fā)了該算法的軟ip核,可以對(duì)所應(yīng)用的擴(kuò)頻碼長(zhǎng)度, a / d采樣后的數(shù)據(jù)量化階數(shù),所用擴(kuò)頻碼等可進(jìn)行隨意改寫。
16. The design of this chip sticks to the general methodology of hdl design . lt is entered in hdl format with innoveda ' s visual hdl and simulated with modelsim simulator , after synthesized with fpga compiler ii , the edif is entered in quartus ii , which is supplied by altera corporation to place and route . the sdo file produced by quartus ii is backannotated to the netlists and timing - simulation is been done . the success of this cryptogrammic chip also shows the effectiveness and advantage of the methodology of high level design with hdl
    在innoveda的visualhdl設(shè)計(jì)平臺(tái)上用hdl語(yǔ)言完成了設(shè)計(jì)輸入，使用modelsim仿真器完成了功能仿真，使用synopsys的fpgacompiler進(jìn)行了基于alterafpga庫(kù)的網(wǎng)表綜合，最后將edif網(wǎng)表輸入altera的布局布線工具quartus中進(jìn)行了布局布線，將生成的sdo文件反標(biāo)到modelsim仿真器中進(jìn)行了時(shí)序仿真，該設(shè)計(jì)的成功，再一次表明了hdl設(shè)計(jì)方法的正確性和有效性。
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