fault coverage

"fault coverage"的翻譯和解釋

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例句與用法

In this paper we investigate and carry out boundary scan ^ internal scan and built - in self - test three dft technologies in the embedded microprocessor estarl and get satisfying result , the fault coverage is more than 96 %
本文針對嵌入式微處理器estar1的結(jié)構(gòu)特點，研究并實現(xiàn)了邊界掃描、內(nèi)部全掃描和內(nèi)建自測試三種可測性設(shè)計技術(shù)，取得了良好的效果，故障覆蓋率達(dá)到96以上。
The results through evaluating the scheme show that under the condition of ensuring high fault coverage , the scheme not only decreases the number of the test vectors by applying an universal test set , but substantially thrifts the extra hardware overhead
經(jīng)過方案評估得出此方案在不降低故障檢測覆蓋率的情況下，既使用通用測試集，又減少測試矢量數(shù)，還大大節(jié)約了附加硬件開銷。
The stuck - open fault is simulated concurrently using iddt testing with the test pattern pairs generated above . through detaching a pattern pair into two independent patterns , the stuck - at fault are simulated concurrently . simulation results show better fault coverage . the
最后,針對iddt測試的可行性,我們通過利用pspice軟件對s208電路中的一些故障做了模擬,這些故障包括開路故障和延時故障。
Internal scan is advanced for the difficulty of fixing the state of sequential circuit , can be divided into full - scan and partial - scan . in this paper we use full - scan according to the real circumstance of estarl and get high fault coverage with very little impact on the circuit
本文根據(jù)estar1的實際情況，設(shè)計實現(xiàn)了全掃描結(jié)構(gòu)，既得到了較高的故障覆蓋率，又對電路的延遲和芯片面積影響很小(延遲時間增加0 . 3 ，芯片面積增加0 . 01 ) 。
Jx5 is a complex microprocessor , which contains cache , microcode rom , instruction prefetch unit , instruction decode unit , integer unit , mmx unit , floating point unit , page unit , bus unit , dp logic , apic and so on . it is very difficulty to test a such complicated microprocessor and receive anticipative fault coverage ratio . so , we must add dft in cpu ’ design
Jx5微處理器是一款結(jié)構(gòu)異常復(fù)雜的微處理器,它的內(nèi)部包含有: cache 、微碼rom 、指令預(yù)取部件和動態(tài)分支預(yù)測部件、指令譯碼部件、整數(shù)部件、多媒體部件、浮點部件、分段和分頁部件、總線接口部件、雙處理器接口部件、可編程中斷控制部件等。
Finally the design of rs decoder in this chip is described as an example of the hardware / software co - design based on asip , the construction and application of asip is also analyzed . the fourth chapter introduces the design flow using eda tools based on standard cell , then it presents the dft of this chip in detail which uses following techniques : full scan , bist and boundary scan to improve the fault coverage
第四章，在對本芯片的基于標(biāo)準(zhǔn)單元eda設(shè)計流程進行了簡要說明基礎(chǔ)上，對本芯片采用的可測試性設(shè)計進行了詳細(xì)的分析和說明，本芯片中有機結(jié)合了多種可測試性設(shè)計技術(shù)：基于全掃描的方式、 bist測試技術(shù)、邊界掃描技術(shù)，保證了很高的測試故障覆蓋率。
In addition , the author also research in general detection optimal algorithm used by fault diagnosis system , these detection optimal algorithm can classify into two types , the first type is that algorithm must be able to find the ptvs ( parallel test vector ) which has the best condensing index p under fault location precision request , these algorithm include woa optimal algorithm , true / compliment optimal algorithm ; the second type is that algorithm must be able to find the ptvs which has the best fault location precision under the condensin index p request . these algorithms include minimum weight value optimal algorithm . but these general detection optimal algorithms have a lot of flaw in test time cost or low fault coverage rate
本文作者還對測試優(yōu)化算法進行仔細(xì)研究，研究結(jié)果表明測試優(yōu)化算法可分為兩類，第一類是在滿足給定故障定位精度的前提下尋找能夠?qū)崿F(xiàn)最優(yōu)緊湊性指標(biāo)p的ptvs (并行測試向量集) ，如true compliment算法；第二類是在滿足給定緊湊性指標(biāo)的前提下尋求能夠?qū)崿F(xiàn)最優(yōu)故障定位精度的ptvs ，如極小權(quán)值優(yōu)化算法，研究結(jié)果還顯示這些常規(guī)的算法存在測試時間長、故障覆蓋率低的缺點。
At present testing method based on current testing has become an important cmos digital integrated circuit testing method which has been accepted widely . in order to improve the fault coverage of the testing to meet the demands of people , the dynamic current ( iddt ) testing was proposed to detect some faults that cannot be detected by other testing methods in the middle 1990 ’ s
90年代中期,人們提出了瞬態(tài)電流測試方法( iddt ) ,以便發(fā)現(xiàn)一些其他測試方法所不能發(fā)現(xiàn)的故障,進一步從總體上提高測試的故障覆蓋率,滿足人們對高性能集成電路的需要。