floating-point arithmetic

"floating-point arithmetic"的翻譯和解釋

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Many embedded applications have little or no need for floating - point arithmetic , and software emulation of powerpc floating - point instruction execution is usually more than adequate when it is needed
很多嵌入式應(yīng)用程序很少或者根本不需要浮點(diǎn)算法，而當(dāng)需要的時候，對powerpc浮點(diǎn)指令執(zhí)行進(jìn)行軟件仿真就足夠了。
Thirdly dct is implemented using chen fast dct algorithm . we transform float - point arithmetic into fixed - point arithmetic , which meeting the precision requirements of the ieee 1180 standard , to accord with fixed - point c6201 dsps
隨后在dct變換編碼中，采用chen快速dct算法，在保證idct精度符合ieee1180標(biāo)準(zhǔn)條件下，將浮點(diǎn)dct系數(shù)轉(zhuǎn)化為與c6201定點(diǎn)dsps運(yùn)算單元相適應(yīng)的定點(diǎn)系數(shù)。
2 montoye r k , hokenek e , runyon s l . design of the ibm risc system 6000 floating - point execution unit . ibm journal of research and development , 1990 , 34 : 59 - 71 . 3 oberman s . floating - point arithmetic unit including an efficient close data path
我們采用90納米cmos標(biāo)準(zhǔn)單元工藝以及synopsys自動布局布線流程進(jìn)行實(shí)驗(yàn)，實(shí)驗(yàn)結(jié)果表明該算法在高性能雙通路結(jié)構(gòu)的浮點(diǎn)加減運(yùn)算中引入后，可以使得近路徑的運(yùn)算延遲整體降低10 . 2 % ，且算法本身沒有造成新的關(guān)鍵路徑。
Floating - point unit is a special microprocessor circuitry unit that deals with floating - point arithmetic operations , which is widely used in scientific arithmetic , cpu , dsp ( digital signal processing ) and image processing , , the thesis discusses how to implement high - performance floating - point processing unit based on the research of its implementation algorithm and its implementation structure
浮點(diǎn)運(yùn)算單元( fpu )是處理器中專門進(jìn)行浮點(diǎn)算術(shù)運(yùn)算的電路單元，廣泛應(yīng)用在科學(xué)計(jì)算、 cpu 、 dsp和圖象處理。論文從浮點(diǎn)運(yùn)算單元的實(shí)現(xiàn)算法和結(jié)構(gòu)的研究出發(fā)，討論如何實(shí)現(xiàn)高性能浮點(diǎn)運(yùn)算單元。
After that , it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler . moreover , this paper explores the method of design the floating - point arithmetic unit . referring to the ieee754 - 1985 standard for binary floating - point arithmetic , the algorithm and the behavior description of floating - point adder and multiplier is given , and the simulation and verification is shown at the end of this paper
此外，本文還對處理器的浮點(diǎn)運(yùn)算單元設(shè)計(jì)做了初步的研究，以ansi ieee - 754浮點(diǎn)數(shù)二進(jìn)制標(biāo)準(zhǔn)為參考，借鑒了經(jīng)典的定點(diǎn)加法器和乘法器的設(shè)計(jì)，嘗試性的給出了浮點(diǎn)加法單元和乘法單元的實(shí)現(xiàn)模型和行為級上的硬件描述，并對其進(jìn)行仿真和驗(yàn)證。