Not only we analyze these architectures ’ efficiency and computing complexity , but also complete the 8 - band parallel processing receiver ’ s computer simulation and fpga realization to testify the architectures are correct and hardware realizable 從結(jié)構(gòu)有效性和運(yùn)算復(fù)雜度對(duì)各種模型進(jìn)行分析和比較,并通過8信道并行處理接收機(jī)的matlab仿真和fpga實(shí)現(xiàn)驗(yàn)證了模型的正確性和可實(shí)現(xiàn)性。
Experimental results show the hidden information capacity of this algorithm is one time more than lsb algorithm , and much more than all kinds of transform domain algorithms , but computing complexity is much lower than transform domain 實(shí)驗(yàn)表明在不影響圖像視覺效果的前提下,其信息隱藏量比lsb算法大一倍以上,比各種變換域算法的信息隱藏量更是大很多,而計(jì)算復(fù)雜度比變換域算法低很多。
( 3 ) it is well known that the determinant problem in classic proposition logic is a np complete problem , and the first order logic is a half determinant one . so both the analysis of computing complexity and the realization of it are the most important fields ( 3 )眾所周知,經(jīng)典命題邏輯中的判定問題是np完全問題,而一階邏輯是半可判定問題,關(guān)于非經(jīng)典邏輯特別是非單調(diào)邏輯的計(jì)算復(fù)雜性分析和算法實(shí)現(xiàn)是一個(gè)重要的研究領(lǐng)域。
Because of the rapid increasingly computing complexity and the explosive growth of information , the traditional centralized computing patterns are not adequate for large - scale distributed information processing , but agent - based computing and high - level interaction may satisfy the modern computing and distributed information processing , and multi - agent system ( mas ) can play an important role in analyzing and developing the model and theory of human - interaction 隨著現(xiàn)代計(jì)算復(fù)雜性和信息量的急劇增長,傳統(tǒng)的集中計(jì)算模式已不能適應(yīng)大型分布式信息處理的發(fā)展。而基于agent的計(jì)算和以agent為主體的高層交互可以滿足現(xiàn)代計(jì)算和分布式信息處理系統(tǒng)的要求,而且多agent系統(tǒng)在分析和建立人類交互模型和交互理論中可以發(fā)揮重要作用。
The comparable results of the barnard - log algorithm show that it has good tolerance of the illumination and contrast . based on this feature extraction , a stereo matching algorithm is implemented to support its efficacy . ( 3 ) to reduce the computing complexity of the cross correlation in the area based stereo matching , an increment based optimized algorithm for ssd and cross correlation algorithm is proposed 然后將該barnard - log特征應(yīng)用到一種特征匹配算法,并通過實(shí)驗(yàn)說明所改進(jìn)的barnard - log特征算法在圖像匹配中具有比較好的適用性; ( 3 )針對(duì)區(qū)域匹配中應(yīng)用圖像互相關(guān)算法和ssd算法計(jì)算復(fù)雜度較高的問題,分別為圖像互相關(guān)算法和ssd ( sumofsquaredifference )算法引入增量方法的思想來降低計(jì)算復(fù)雜度。
A relation between packet loss rate and times of simulating decoding in encoder was setup in proposed algorithm for the first time . using this relation , encoder could adaptively determine the times of simulating decoding according packet loss rate and the number of simulating channel states . so the computing complexity and coding time in encoder was decreased effectively 該算法首次在當(dāng)前信道丟包率與編碼器端進(jìn)行仿真解碼的次數(shù)之間建立起了一種對(duì)應(yīng)關(guān)系,根據(jù)此對(duì)應(yīng)關(guān)系編碼器端可根據(jù)當(dāng)前信道丟包率信息以及模擬隨機(jī)信道狀態(tài)的個(gè)數(shù)來自適應(yīng)地決定進(jìn)行仿真解碼的次數(shù),從而有效降低編碼器端的計(jì)算量和編碼耗時(shí)。
Based on knowledge reasoning , fuzzy theory , extraction of sub - assembly and cluster , and hierarchical connection relation graph , an assembly sequence generation algorithm is studied in this paper , which breaks down the original complex assembly sequence generation problem into several small scale assembly sequence planning problems to reduce the computing complexity caused by cut - set theory . a hierarchical and / or graph to store all the generated sequences is also employed for this purpose 本文提出基于知識(shí)推理及模糊理論,結(jié)合子裝配與聚族提取以及裝配樹,利用層次聯(lián)接關(guān)系圖,將一個(gè)復(fù)雜的裝配序列求解問題轉(zhuǎn)化為若干個(gè)相關(guān)的小規(guī)模裝配序列求解問題,并用一種層次與或圖結(jié)構(gòu)存儲(chǔ)裝配序列,使割集法求解裝配序列的計(jì)算復(fù)雜度大大降低。
By introduce new video coding technologies , avs and h . 264 gain a wonderful coding efficiency . the computing complexity also increases for 2 - 3 times than mpeg - 2 because of the complexity of the algorithm . that means the performance of software decoding can not achieve a high level , especially the real - time high - definition decoding 同時(shí)avs和h . 264等高級(jí)視頻編碼標(biāo)準(zhǔn)采用了大量最新的視頻編碼技術(shù),獲得了很好的效果,但是其壓縮效率的提高也是以壓縮算法復(fù)雜度的提高為代價(jià)的,其解碼復(fù)雜度大約是mpeg - 2的2 - 3倍,這造成了單純用軟件解碼難以達(dá)到很高的性能,特別是對(duì)于實(shí)時(shí)應(yīng)用,對(duì)于高清晰度視頻不能實(shí)現(xiàn)實(shí)時(shí)解碼,這樣就需要硬件加速或者設(shè)計(jì)專門的硬件解碼電路。
Follow aspects are discussed in this thesis and effective solutions are proposed . architecture of video decoding soc the computing complexity of video decoding is analyzed in this thesis and a reasonable and feasible scheme is proposed . a hardware module partitioning also be proposed based on the comparison of different method 本文針對(duì)以下幾個(gè)問題作了詳細(xì)研究,并提出了有效的解決方案:視頻解碼soc結(jié)構(gòu)設(shè)計(jì)本文分析了視頻解碼的計(jì)算復(fù)雜度,進(jìn)行了合理可行的軟硬件劃分,并在比較不同方案的基礎(chǔ)上,進(jìn)行了合理的硬件模塊劃分。
In order to reduce the computing complexity and the needed data storage , some fast algorithm of the decoding flow are studied , the idct module in the synthesizer subband filters is discussed detailed . a algorithm of idct implement on the fixed - point dsp chip is given 論文最后對(duì)解碼流程呻的大運(yùn)算量模塊進(jìn)行了研究,重點(diǎn)針對(duì)子帶綜合濾波器中的idct運(yùn)算進(jìn)行改進(jìn),提出一種基于定點(diǎn)dsp的快速算法,降低了程序的計(jì)算量和數(shù)據(jù)存儲(chǔ)量,并在定點(diǎn)數(shù)字信號(hào)處理芯片上得到實(shí)現(xiàn)。