fft algorithm

"fft algorithm"的翻譯和解釋

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In this paper , the design and implementation of real - time image capture board based on tms320c6205 dsp ( digital signal processor ) for plate recognition and fft algorithm is studied . also , the methodology for hand - coding algorithms and software pipelines for tms320c6205 vliw - type processors are proposed for improving the code efficiency . last , the optimized methods for realizing plate recognition system and fft are applied
本文用基于tms320c6205數(shù)字信號處理器的實時圖像處理板來實現(xiàn)牌照識別系統(tǒng)以及fft算法，主要包括： 1 )自行設(shè)計和制作了實時圖像處理板2 )提出了針對tms320c6205vliw結(jié)構(gòu)的手動編碼方法以及流水線實現(xiàn)方法，用以提高代碼的效率3 )提出了針對牌照識別系統(tǒng)和fft算法的優(yōu)化方法。
The concept , advantages and history of bistatic isar are introduced first in this paper , then 2 - d turntable imaging of monostatic isar the special example of bistatic isar is studied . on the basis of monostatic isar four imaging algorithms are analyzed , including fft algorithm , filtered backprojection algorithm , spectrum extrapolation algorithm and esprit algorithm , and compared in the small and big angel of imaging . on the basis of monostatic imaging the 2 - d turntable imaging principle of bistatic isar is studied ,
本文首先闡述了雙站逆合成孔徑雷達(dá)的概念、優(yōu)點和發(fā)展歷程,然后研究了雙站逆合成孔徑雷達(dá)的特例? ?單站逆合成孔徑雷達(dá)對轉(zhuǎn)臺目標(biāo)的二維成像算法,并在此基礎(chǔ)上分析了四種主要的轉(zhuǎn)臺成像算法, fft算法、濾波逆投影算法、譜外推算法和esprit算法,并對以上各種算法分別在小角度和大角度下的成像性能進行了比較。
It summarizes the basic conceptions of image compress processing , parallel processing technique and parallel algorithm briefly . then it emphasizes on the network parallel computing environment and logp model of parallel computation . this paper describes the methods of developing parallel algorithm and applications through the designing , analyzing , optimizing , and implementing of digital image processing parallel algorithm , include fft algorithm , wavelet transform , medium filtering , binary image algorithm etc
本文概述了并行處理技術(shù)和圖像壓縮技術(shù);并詳細(xì)闡述了并行算法及圖像處理算法的基本概念和模型;詳細(xì)討論了網(wǎng)絡(luò)并行l(wèi)ogp模型及并行算法的開發(fā)環(huán)境;并進行了fft并行編碼算法、小波并行編碼算法,中值濾波,圖像二值化等圖像處理的并行算法的設(shè)計與分析。
The key to the fft algorithm is the design of butterfly computation and that of the address logic . the whole schema is designed in the top - down design flow and described in the vhsic hardware description language ( vhdl ) , basing on these , we do our research on reconfigurable technology . the result indicates that the data processing ability of reconfigurable system improved greatly
結(jié)果表明，可重構(gòu)系統(tǒng)在數(shù)據(jù)處理能力方面比以往的系統(tǒng)有了很大的提高，本設(shè)計實現(xiàn)的fft重構(gòu)處理器可工作于60mhz下，完成一個16點fft需要132個主時鐘周期，完成32點fft需要324個主時鐘周期，而且具有一定可重構(gòu)性，可以方便地將其運算點數(shù)進行擴展，或?qū)⑵渌膱D像處理算法在實時處理系統(tǒng)中實現(xiàn)。