programmable gate array中文是什么意思

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中文翻譯
造句

可編程序門陣列

gate gate2 n. 1.〔古語〕街道，路〔一般 ...
array vt. 1.打扮，裝飾。 2.使…列隊，排列。 3.提出 ...
array programmable gate 可編程門陣列
array, programmable gate (pga) 可編程門陣列
field programmable gate array 可現(xiàn)場編程門陣列; 現(xiàn)場可編程邏輯陣列
filed programmable gate array 現(xiàn)場可程式閘門陣列
pga programmable gate array 可編程門陣列
programmable gate array (pga) 可編程門陣列
antifuse field programmable gate array 反熔絲可現(xiàn)場編程門陣列
array, antifuse field programmable gate 反熔絲可現(xiàn)場編程門陣列
array, field programmable gate (fpga) 可現(xiàn)場編程門陣列
field programmable gate array, fpga 現(xiàn)場可編程門陣列
fpg field programmable gate array 現(xiàn)場可編程
fpga field programmable gate array 現(xiàn)場可編程門陣列
mpga mask programmable gate array 掩模可編程門陣列
programmable array 可編程序陣列
programmable gate 程序可控門; 程序控制門
array, gate 門陣列
gate array 門數(shù)組; 門陣列; 柵陣列
array programmable logic 可編程邏輯陣列
array, programmable logic (pla) 可編程邏輯陣列
field programmable logic array 現(xiàn)場編程邏輯陣列; 現(xiàn)場可編程序的邏輯陣列; 現(xiàn)場可編程序邏輯陣列
field-programmable logic array 場程序邏輯陣列; 場致程序邏輯陣列
fuse programmable array logic 熔絲燒斷可編程序邏輯陣列
logic multiple array programmable 多重陣列可編程邏輯

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例句與用法

Fpga ( field programmable gate arrays ) is a new type of ic ( integrated circuit ) in recent years . it has advantages of compactness 、 economy 、 high speed 、 low consumption 、 full integration and good applicability . it is easy to be developed and be maintained
現(xiàn)場可編程門陣列器件( fieldprogrammablegatearrays )是近年來嶄露頭角的一類新型集成電路,它具有簡潔、經濟、高速度、低功耗等優(yōu)勢,又具有全集成化、適用性強,便于開發(fā)和維護(升級)等顯著優(yōu)點。
In view of numerous digital and analog signals need to be processed , and the difficulty of real - time processing of multi channel 400 hz ac signal , vhdl ( vhsic hardware description language ) is applied to design the digital circuit , which is successfully realized in field programmable gates array ic - xc2s100
針對i o模塊中需要處理的數(shù)字量和模擬量較多的事實，以及多路400hz信號的實時處理較為繁重的現(xiàn)狀，作者采用了現(xiàn)場可編程門陣列( fpga )加以解決。
After the investigation of the general technology of hardware implementation , how to implement the kasumi algorithm using field programmable gate array ( fpga ) device is discussed in detail , and the author develops the cipher chip of kasumi algorithm , the kasumi cipher card based on 32 - bits pci bus , the wdm device driver that used in windows2000 / xp , and the software to demostrate encrypting data link . finally , an application demostration is constructed with all the above implementation
在此硬件實現(xiàn)的結果芯片基礎上，設計了32位的基于pci總線的kasumi加密卡，編寫了windows2000 xp下的windows驅動程序模型( wdm )驅動程序和鏈路加密應用程序，由此構成一個應用演示系統(tǒng)，作為研制結果的應用評估，為進一步進行第三代移動通信系統(tǒng)相關安全技術研究和開發(fā)提供了基礎條件。
Because period narrow band signals are the main part of background noises , this thesis uses hardware description language to design a multi - band finite impulse response filter ( fir ) and downloads the program into filed programmable gate array to eliminate the period narrow - band interferences in the background noises
3 )在現(xiàn)場環(huán)境中，背景干擾主要是周期性的窄帶，本文利用硬件描述語言( vhdl )設計了一個多帶fir有限沖擊響應濾波器。應用到可編程邏輯器件中，消除了背景噪聲中的周期性干擾，為信號的進一步處理提供盡可能干凈的信號。
Finally , on the basis of the mpeg - 1 layer hencoding hardware structure , the block of logic communicates with the pc over the parallel port and the interface for flash memory are design . then a mpeg audio coding system , which applies to store audio signal , is presented through the field programmable gate array device technology
最后，在mpeg - 1層編碼的硬件結構的基礎上，結合計算機并口通信和flash存儲器的接口模塊，采用現(xiàn)場可編程邏輯器件fpga技術，最終設計了一種應用于音頻信號存儲的mpeg音頻編碼系統(tǒng)。
With the development of electronic and eda ( electronic design automatic ) technology , large scale integration can be replaced by pld ( programmable logic device ) and fpga ( field programmable gates array , which can realize the function of the programmable interface chip and many different programmable interface chips
隨著電子技術和eda技術的發(fā)展，大規(guī)模可編程邏輯器件pld ( programmablelogicdevice ) 、現(xiàn)場可編程門陣列fpga ( fieldprogrammablegatesarray )完全可以取代大規(guī)模集成電路芯片，實現(xiàn)計算機可編程接口芯片的功能，并可將若干接口電路的功能集成到一片pld或fpga中。
With rapid developments of system on chip ( soc ) , programmable logic devices ( pld ) , including complex programmable logic device ( cpld ) and field programmable gate array ( fpga ) , can support in - system programmability ( isp ) and become more popular in the world . this requires better download cables than before , which are used to program plds
隨著片上系統(tǒng)( soc , systemonchip )時代的到來,包括復雜可編程邏輯器件( cpld , complexprogrammablelogicdevice )和現(xiàn)場可編程門陣列( fpga , fieldprogrammablegatearray )的可編程邏輯器件,具有系統(tǒng)內可再編程的獨特優(yōu)點,應用越來越廣泛。
In order to meet the requirement of real time of system , modularization configuration and dsp + fpga is used for realizing parallel processing of signal in system hardware . the implementation of fft algorithms is performed by field programmable gate arrays ( fpga ) , and spectrum analysis is done by dsp , and at the same time , sequence control of entire system is performed by cpld
為滿足系統(tǒng)實時性要求,系統(tǒng)硬件電路采用模塊化結構,利用快速的dsp + fpga實現(xiàn)信號的并行處理,采用fpga實現(xiàn)fft算法,使用dsp完成譜信號的分析,同時通過cpld來完成整個系統(tǒng)時序的控制。
The design of hardware is based on fpga ( filled programmable gate array ) and mcu ( micro computer unit ) , providing small volume , reliability and simply control . the design of software is based on keil c51 and foundation 3 . 1 . it can realize many complex functions , so the flexibility of application is greatly strengthened
數(shù)據(jù)采集卡的硬件設計基于現(xiàn)場可編程門陣列（ fpga ）和單片機（ mcu ），體積小、工作可靠、控制簡單、外圍電路少；軟件設計采用keilc51和foundation3 . 1 ，可根據(jù)用戶需要實現(xiàn)多種復雜的功能，極大的提高了應用的靈活性。
In this dissertation , the method to design and realize the digital receiver in the field programmable gate array ( fpga ) has been discussed ; combining coordinate rotation digital compute ( cordic ) to design nco , we get a efficient structure without multiplications
本論文正是運用現(xiàn)場可編成邏輯器件( fpga )設計與實現(xiàn)數(shù)字接收機問題開展研究,結合坐標旋轉數(shù)值計算( cordic )算法實現(xiàn)數(shù)控振蕩器( nco ) ,得到一種免乘法器高效可移植性好的數(shù)字接收機fpga實現(xiàn)結構,并在現(xiàn)有的硬件平臺上進行了接收機系統(tǒng)的調試,測試結果表明該接收機能夠達到系統(tǒng)指標要求。

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