synthesis tools中文是什么意思

發(fā)音:

中文翻譯
造句

邏輯綜合工具

synthesis n. (pl. -ses ) 綜合，【化學(xué)】合成；【邏輯 ...
tool n. 1.工具，用具，器具；【機(jī)械工程】刀具；工具母機(jī) ...
tools 裝配工具
for synthesis 合成用
synthesis n. (pl. -ses ) 綜合，【化學(xué)】合成；【邏輯學(xué)】綜合(法)；【語(yǔ)言學(xué)】綜合(性)；語(yǔ)詞的合成；【醫(yī)學(xué)】接合；【物理學(xué)】合成綜合。
abrasive tools 研磨工具
advanced tools 高級(jí)工具（什么工具？我沒覺出來(lái)）
air tools 風(fēng)動(dòng)工具; 氣動(dòng)工具
aligning tools 校準(zhǔn)工具
alignment tools 校直工具
analysis tools 刀軌分析工具; 分析工具
analytic tools 分析工具
animation tools 動(dòng)畫工具
are tools location 手工備品倉(cāng)
artisan’s tools 工匠工具
assembly tools 裝配工具
authoring tools 條目項(xiàng)下，列出了制作工具; 著作工具
auxiliary tools 輔助儀表
bar tools 用具
bibliographic tools 目錄工具書
bibliographical tools 查目工具, 資料檢索工具
bit tools 刀具
blasting tools 爆破工具
bone tools 骨骼工具
bricklayers tools 泥瓦工工具

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例句與用法

High level synthesis tool can choose best scheme in a large design space
高級(jí)綜合工具可以在很大的設(shè)計(jì)空間中選擇最優(yōu)的設(shè)計(jì)方案。
Automatic synthesis tool after validation can eliminate error because of manual work
采用經(jīng)過(guò)驗(yàn)證的自動(dòng)綜合工具，可以消除大部分可能由人工帶來(lái)的設(shè)計(jì)錯(cuò)誤。
The program deriving dynamic equations runs in puj 800 , double cpu , 256 mb memory . the synthesis tool and cmos chip of xilinx company are applied to design the hardware
本文中的動(dòng)力學(xué)方程推導(dǎo)程序是在p 800 ，雙cpu ， 256兆內(nèi)存的機(jī)器上運(yùn)行的。硬件的設(shè)計(jì)是采用xilinx公司的綜合工具與芯片實(shí)現(xiàn)的。
Lastly , we use the high level synthesis tool synplify to test the validity of the improving mcu . according to the synthesis result , the system clock reached about 66mhz
最后,采用synplicity公司的高層綜合工具synplify對(duì)所設(shè)計(jì)的mcu進(jìn)行了綜合,綜合結(jié)果驗(yàn)證了改進(jìn)型mcu滿足了要求,工作頻率達(dá)到66mhz 。
We implement des algorithm and 1024 - bit rsa algorithm with verilog hdl , and simulate their fpga implementation with modisim synthesis tool . finally we test the correctness and performance of the implementation method
采用veriloghdl語(yǔ)言編程實(shí)現(xiàn)了des算法和1024位rsa算法,并在modelsim綜合仿真工具中對(duì)算法的fpga實(shí)現(xiàn)方法進(jìn)行了仿真,檢驗(yàn)了算法實(shí)現(xiàn)方法正確性和性能。
The circuit is synthesized by synplify pro which is synplicity ' s synthesis tool and emulated by quartus ii which is altera ' s developing tool , which has proved the feasibility and correctness of the circuit
采用硬件描述語(yǔ)言vetilog編寫了硬件電路程序，并使用synplicity的綜合工具synplifypro和altera開發(fā)工具quartus對(duì)電路系統(tǒng)進(jìn)行了綜合與仿真驗(yàn)證，證明了硬件電路的可行性與正確性。
I described the principles - . characteristics > function ^ system structure and design flow of synthesis in detail o although synthesis tool does an excellent job of converting hdl to gates . the structure of the hdl may not allow tool to meet the designer - specified constraints and very likely to result in an increase in compile time . the startpoint for synthesis affects the quality of results after synthesis , thus , to attain good startpoint the paper presented a lot of coding styles
本文回顧了集成電路設(shè)計(jì)方法學(xué)的發(fā)展，提出了它們的共同點(diǎn)是基于綜合的設(shè)計(jì)思想，詳細(xì)地介紹了綜合的基本原理、特點(diǎn)、作用、綜合的系統(tǒng)結(jié)構(gòu)及設(shè)計(jì)流程；同時(shí)，雖然各公司提供的綜合工具能很好地進(jìn)行從hdl級(jí)的描述到門級(jí)的轉(zhuǎn)換，但是hdl的結(jié)構(gòu)有時(shí)會(huì)導(dǎo)致綜合的結(jié)果難以滿足預(yù)先的要求和綜合時(shí)間的增加，所以hdl的編碼風(fēng)格對(duì)綜合結(jié)果的影響很大。
Gae is basically a browser - server argumentation system , which supports loosely coupled group ' s activities , including group thinking and group decision modules , called knowledge creation tool and knowledge synthesis tool respectively . knowledge creation tool supports experts divergent thinking and qualitatively analyzing complex problems
基于web的b / s結(jié)構(gòu)的松散耦合的gae系統(tǒng)給用戶提供一個(gè)集約化知識(shí)支持平臺(tái)，系統(tǒng)包括支持群思考和群決策的兩個(gè)模塊，分別是知識(shí)創(chuàng)造的發(fā)散工具和知識(shí)綜合的收斂工具。
The characteristic of this ba is applying the dual scaling method to visualize the experts " argumentation contents , which can encourage participation , facilitate users assimilate others ideas , and stimulate emergence of more creative ideas . knowledge synthesis tool applies the ahp and ngt method , which are convergent method , to quantitatively testify the structure problems . in a word , gae system is an environment for solving complex problems
發(fā)散工具是專家發(fā)散思考，定性分析復(fù)雜問題的“場(chǎng)” ，特點(diǎn)是應(yīng)用雙尺度法( dualscalingmethod )將專家研討內(nèi)容加以可視化分析，這種二維圖的表現(xiàn)形式刺激了專家進(jìn)一步思考，拓寬其思維，幫助他們多視點(diǎn)、多角度、多側(cè)面去了解所要解決問題的目標(biāo)。
This design for mvbc system adopts top - down eda common design flow . circuit design adopts veriloghdl coding description . function simulation and timing verification adopt simulation tool vcs of synopsys inc , the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc , and the fpga advice stratix ii ep2s15
該mvbc系統(tǒng)設(shè)計(jì)采用業(yè)界通用的自上而下的eda設(shè)計(jì)方法,電路邏輯實(shí)現(xiàn)采用veriloghdl硬件語(yǔ)言描述,功能和時(shí)序驗(yàn)證的動(dòng)態(tài)仿真采用synopsys公司的vcs ,而邏輯綜合與fpga實(shí)現(xiàn)采用altera公司的集成開發(fā)環(huán)境quartusii軟件以及stratixiiep2s15的fpga器件。

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