定時(shí)算法的英文

定時(shí) timing; at regular time; fix ...
算法 algorithm
超時(shí)算法 time out algorithm
實(shí)時(shí)算法 real-time algorithm
實(shí)時(shí)算法試驗(yàn)器 real-time algorithmic tester
分時(shí)算符 time-shared operator
結(jié)帳時(shí)算表 closing trial balance
定時(shí) timing; at regular time; fixed time 飲食定時(shí) have one's meals at regular time; 定時(shí)定點(diǎn) at a fixed time and location [place]; 定時(shí)表 timing indicator; 定時(shí)操作 fixed cycle operation
算法 algorithm◇算法語(yǔ)句 algorithmic statement; 算法語(yǔ)言 algorithmic language (algol)
演算法 [算法 algorithm
不定時(shí) untime; variable interval
定時(shí)表 timing indicator; timing meter
定時(shí)波 timing wave
定時(shí)的 periodic; regular; timed
定時(shí)點(diǎn) i timing point; ttiming point
定時(shí)閥 tarry valve; time-limit valve; timing valve
定時(shí)桿 timing lever
定時(shí)軌 track timing
定時(shí)計(jì) tg; timing gage
定時(shí)間 time
定時(shí)孔 timing hole
定時(shí)鏈 camshaft chain; timing chain; timing-chain
定時(shí)門(mén) time gate
定時(shí)盤(pán) timing disc; timing disk
定時(shí)器 timer; keyer; intervalometer; timing device

千萬(wàn)人都在用的超大詞匯詞典翻譯APP

Retiming has been used for many fields recently . regretfully , the retiming algorithm can not be used together with existing combinational optimization techniques
遺憾的是，以前提出的重定時(shí)算法不能很好地與組合優(yōu)化方法結(jié)合起來(lái)。
A retiming algorithm fam which based on simple retiming is introduced in the paper , the time computation complexity of the algorithm is better than the classical algorithm feas
本文在基于簡(jiǎn)單重定時(shí)的基礎(chǔ)上提出了一種重定時(shí)算法fam ，此算法的時(shí)間計(jì)算復(fù)雜度較經(jīng)典算法feas有所改善。
But , retiming should be used together with existing combinational optimization techniques and form an optimizational flow in practical circuitry system to exert fully the advantage of both
而實(shí)際的電路優(yōu)化系統(tǒng)應(yīng)該將重定時(shí)算法與其它組合優(yōu)化方法結(jié)合在一個(gè)優(yōu)化流中，充分發(fā)揮二者的優(yōu)勢(shì)。
In order to eliminate the sequence conflict of synchronous sequential circuit and shorten the designable time of integrated circuits , the algorithms of retiming is deeply researched in this paper
本文對(duì)重定時(shí)算法進(jìn)行了深入研究，目的在于消除同步時(shí)序電路的時(shí)序沖突，從而縮短集成電路的設(shè)計(jì)時(shí)間。

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