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board-level中文是什么意思

  • 插件板級(jí)的

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  • 例句與用法
  • Board - level design for testability based on jtag
    的板級(jí)可測(cè)試性設(shè)計(jì)
  • Application of boundary scan technique to the design for board - level test
    邊界掃描技術(shù)在板級(jí)可測(cè)性設(shè)計(jì)中的應(yīng)用
  • To that end , a demonstrable board - level commitment to an effective formal quality management system must exist
    為此,公司高層必須為一個(gè)有效正式的質(zhì)量管理體系提供可以證明的承諾。
  • Using visual c + + , a board - level test vector generation and fault diagnoses software were designed and carried out
    在visualc + +環(huán)境下,設(shè)計(jì)并實(shí)現(xiàn)了板級(jí)測(cè)試矢量生成軟件和故障診斷軟件。
  • The results show that the viscoelasticity of pcb and its size have distinct influence on dynamic properties of pcb under board - level drop impact
    結(jié)果表明,電路板的黏性系數(shù)和尺寸對(duì)板的動(dòng)力學(xué)特性有顯著影響。
  • Otherwise , by using some board - level test theories and methods , a test resolution , including bst infrastructure integrity test , interconnect test and cluster test was given
    另外,結(jié)合板級(jí)測(cè)試的相關(guān)理論和方法,提出了一套板級(jí)測(cè)試解決方案,包括掃描鏈完整性測(cè)試、互連測(cè)試和簇測(cè)試。
  • He holds a post - graduate degree in business computing , besides having board - level experience in corporate communications , bid management , business development , corporate finance , and information technology
    他擁有商業(yè)計(jì)算機(jī)專(zhuān)業(yè)的碩士學(xué)位,同時(shí)在企業(yè)通訊、招標(biāo)管理、業(yè)務(wù)發(fā)展、公司融資、信息科技等行業(yè)均擔(dān)任過(guò)董事職位。
  • Indeed , most directors are unaware of the growing body of knowledge that is now available about the work of directors , board - level effectiveness and the exercise of power of the modern corporate entity - what is now called corporate governance
    事實(shí)上,大部分董事都不知道現(xiàn)時(shí)有一門(mén)發(fā)展迅速、稱(chēng)為公司管治的學(xué)科。這門(mén)學(xué)科專(zhuān)門(mén)研究有關(guān)董事職務(wù)、董事局的工作效率、現(xiàn)代化公司組織的權(quán)力運(yùn)用等。
  • Followed above , this dissertation has much content about the hardware design which include dsp , fpga , ddr sdram memory bank interface circuit , pci , power circuit , board - level interconnection design . this part puts much emphasis on key circuits many of which require us to have deeply known the components adopted and involved specifications
    這部分主要是對(duì)電原理圖的重要地方和需要注意的地方進(jìn)行重點(diǎn)闡述,包括dsp 、 fpga 、 ddrsdram內(nèi)存條接口電路、 pci接口電路、電源、板級(jí)互連等部分。
  • Then a comparison is made according to their characters and the application scope of each method is determinate . from that we get the whole scheme of design for testability of dspc50 , which is using boundary scan to improve the board - level testability of the chip and using full - scan in designing the nuclear circuit to reduce the difficulty of testing the chip
    在此基礎(chǔ)上得到dspc50的可測(cè)性設(shè)計(jì)的整體方案,即采用邊緣掃描設(shè)計(jì)提高芯片在板級(jí)的可測(cè)性,同時(shí)用全掃描思想設(shè)計(jì)芯片核心電路,以降低芯片本身測(cè)試的難度,即將芯片的全掃描設(shè)計(jì)包含入邊緣掃描系統(tǒng)。
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