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functional simulation中文是什么意思

  • 功能仿真
  • 功能模擬
  • 函數(shù)模擬

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  • 例句與用法
  • Study on wire insulation flammability at microgravity by functional simulation method
    功能模擬微重力下導(dǎo)線的可燃性
  • At last , it gives the corresponding functional simulation result and timing simulation result
    最后給出了相應(yīng)的功能仿真和時(shí)序仿真結(jié)果。
  • The main processes include system partition , module design and functional simulation
    主要步驟包括:系統(tǒng)的劃分,模塊的設(shè)計(jì)和功能的仿真。
  • Through the arithmetic , we can assemble and combine fuzzy rules gained by neural networks automatically . furthermore we test its effectiveness by functional simulation experiment
    利用這種算法,可以將由神經(jīng)網(wǎng)絡(luò)自動(dòng)獲取的模糊規(guī)則進(jìn)行合并與調(diào)整,并通過(guò)一個(gè)函數(shù)的仿真實(shí)驗(yàn)驗(yàn)證了算法的有效性。
  • The whole circuit consists of a multiplier , an error amplifier , a comparator , a rs flip - flop , an and gate , and an inverter , etc . . the electronic circuit simulator cadence is utilized to practice the detailed functional simulation of the general circuit and the subsystem circuits
    整個(gè)電路由模擬乘法器、誤差放大器、比較器、 rs觸發(fā)器、與門和倒相器等基本單元電路組成,采用工作站上的大型ic設(shè)計(jì)軟件cadence進(jìn)行仿真。
  • Except for design methodology and technique , some comprehensive experiments are performed . these experiments use some eda tools , including functional simulation with cadence ' s verilog xl , logic synthesis with synopsys ' s design compiler
    本文除了介紹的設(shè)計(jì)方法和設(shè)計(jì)技巧,還做了一些有益的實(shí)驗(yàn),使用到許多流行的eda工具,如cadence公司的verilog - xl 、 siliconensemble , synopsys公司的designcompiler 、 physicalcompiler等。
  • Design and implementation of a fast round robin scheduler , in which a pipelined barrel shifter and a pipelined priority encoder are used ; testbench development of functional simulation for module verification and system verification , in which the bfm simulation model are used and some reference examples are proposed ; discussing the questions that should be paid attention to when using fpga to design high speed circuits and some design skills ; taking part in the system ' s integration and fpga implementation ; taking part in the system ' s test and verification ; the design of this thesis has provided some key method for inter - communication among different network processors , and also accelerated the development of communication products
    討論了用fpga設(shè)計(jì)高速電路應(yīng)注意的問(wèn)題和一些常用的設(shè)計(jì)技巧;參與整個(gè)轉(zhuǎn)換邏輯的系統(tǒng)集成和fpga實(shí)現(xiàn);參與系統(tǒng)的驗(yàn)證工作;通信協(xié)議轉(zhuǎn)換邏輯的設(shè)計(jì)不僅可以解決不同網(wǎng)絡(luò)處理器之間互通的問(wèn)題,而且對(duì)于促進(jìn)國(guó)產(chǎn)數(shù)據(jù)通信產(chǎn)品的研究與開發(fā)具有很重要的意義。同時(shí)在設(shè)計(jì)的過(guò)程中,進(jìn)一步地探討了基于fpga的高速電路設(shè)計(jì)技術(shù),對(duì)于fpga的設(shè)計(jì)有參考價(jià)值。
  • It is important to study the probability of detection when evaluating the filtering algorithm by simulation , in this paper , the simulation model of radar ' s measurement data is developed using the radar ' s functional simulation method , also we have presented the probability of detection under some typical ecm situation
    利用仿真的方法來(lái)評(píng)價(jià)算法的性能時(shí),計(jì)算雷達(dá)的檢測(cè)概率是很重要的研究?jī)?nèi)容。本文利用雷達(dá)的功能仿真方法建立了電子戰(zhàn)條件下雷達(dá)的觀測(cè)模型,給出了幾種典型的電子對(duì)抗條件下的檢測(cè)概率計(jì)算方法。
  • This thesis focuses on the ingress process module of ctu , which translates c - 5 dcp format to rainier 4gs3 . the specification analysis , architecture and logic design , functional simulation testbench design , synthesis report and testing result are discussed in this thesis . the research work mainly includes : the specification analysis and design requirements of ctu logic ; the architecture and logical design of ingress process module , which includes receive control fsm , send control fsm and cell position adjustment logic ; the performance improvement of ingress process module to receive and transmit data cell at the full line speed
    本論文的主要研究工作包括:通信協(xié)議轉(zhuǎn)換邏輯的功能分析和設(shè)計(jì)需求;通信協(xié)議轉(zhuǎn)換邏輯上行方向的系統(tǒng)分析及體系結(jié)構(gòu)設(shè)計(jì),包括上行接收狀態(tài)機(jī)、發(fā)送狀態(tài)機(jī)、信元內(nèi)字節(jié)位置調(diào)整機(jī)制等的設(shè)計(jì);通信協(xié)議轉(zhuǎn)換邏輯上行方向的線速設(shè)計(jì),主要是上行接收的線速設(shè)計(jì),要使用流水設(shè)計(jì)技術(shù);提出了高速實(shí)現(xiàn)roundrobin調(diào)度策略的實(shí)現(xiàn)方法,并設(shè)計(jì)實(shí)現(xiàn)了桶式移位器和優(yōu)先級(jí)編碼電路;應(yīng)用bfm仿真模型設(shè)計(jì)了上行處理各模塊的仿真testbench ,完成了各級(jí)模塊的模塊仿真和系統(tǒng)集成仿真。
  • There ’ re two parts in the thesis : the design and implementation of fpga module and the design and implementation of the aes digital audio i / o circuit . i use xilinx corporation ’ s ise4 . 2 as development tools to carry on fpga design , including hdl coding , functional simulation , logic synthesis , place & route and generation of programming files . fpga is used to implement audio routing , sine wave , adc ’ s calibration and led etc , . also , i have downloaded the configuration program into fpga chipset using mcu . eventually , the device is tested and the requirements of design is met
    通過(guò)測(cè)試, etheraudio音頻路由器完全達(dá)到了設(shè)計(jì)要求。 etheraudio音頻路由器完全符合aes / ebu硬件規(guī)范,滿足專業(yè)音頻傳輸、路由需求。最后,本文還介紹了etheraudio音頻路由器在廣播電臺(tái)中的應(yīng)用實(shí)例,通過(guò)分析該音頻路由器在廣播電臺(tái)的應(yīng)用方式說(shuō)明本課題的實(shí)際應(yīng)用價(jià)值。
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