A transaction - based verification methodology ( tbv ) can be the most effective method to make functional verification 大量實(shí)踐證明,基于事務(wù)的驗(yàn)證重用方法學(xué)是提高功能驗(yàn)證效率的最有效的方法之一。
Based on the tbv methodology , a framework for functional verification automation solution is proposed in this dissertation . the main works are as follows : 1 本論文在該方法學(xué)基礎(chǔ)上,完成了一個(gè)soc功能驗(yàn)證自動(dòng)化系統(tǒng)的設(shè)計(jì)與實(shí)現(xiàn),主要工作如下: 1
It discusses the architecture of testbench in functional verification of dtv chip and detailed accounts realization of memory bist ( build in self test ) method 本章介紹了各種主流驗(yàn)證測試方法,著重?cái)⑹隽薲tv芯片中功能驗(yàn)證的平臺(tái)結(jié)構(gòu)設(shè)計(jì)和存儲(chǔ)器內(nèi)建式自測試( bist )的具體實(shí)現(xiàn)。
This paper emphasizes on functional verification research . these research results are implemented to verify 8 - bit risc , which has been designed by our institute and has been named hgd08r01 本文的重點(diǎn)就是研究功能驗(yàn)證,其研究成果已成功地運(yùn)用在我所自行設(shè)計(jì)的8位risc核? ? hgd08r01 。
Ieee trans . computers , may 1992 , 41 : 654 - 659 . 18 fallah f , devadas s , keutzer k . occom - efficient computation of observability - based code coverage metrics for functional verification 該方法采用變量的賦值和引用作為可觀測性分析的基礎(chǔ),可以很容易地與其它考慮可控制性的覆蓋準(zhǔn)則相結(jié)合。
A layout inspection and a functional verification to applicable customer engineering material and performance standards shall be performed for each product as specified in the control plans 必須按控制計(jì)劃的規(guī)定,按適用的顧客工程材料及性能標(biāo)準(zhǔn),對每個(gè)產(chǎn)品進(jìn)行全尺寸檢驗(yàn)和功能驗(yàn)證。
And the process of functional verification consists of the implementation of rtl ( register transfer level ) simulation , gate level simulation and post - layout simulation in the process of design 驗(yàn)證最關(guān)鍵的是測試方案的制定,而功能驗(yàn)證的過程是在于在設(shè)計(jì)過程中實(shí)施rtl級(jí)仿真、門級(jí)仿真和后仿真。
Both hardware and the embedded software should be verified together , the performance of simulator decreased dramatically . as a result , functional verification has become the dominant resource issue in developing soc 針對系統(tǒng)芯片的驗(yàn)證也變得非常困難,不但要對硬件進(jìn)行驗(yàn)證,還要對運(yùn)行在嵌入式處理器中的軟件進(jìn)行聯(lián)合驗(yàn)證。
Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?