To increase hardware utilization and minimize cost , we combine inter and intra prediction by a reprogrammable fir filter , which is further implemented with systolic array 利用在解碼的過程中一個巨塊不會同時利用到內(nèi)部以及相互預(yù)測的特性,設(shè)計了一套既可以處理內(nèi)部預(yù)測也可以處理相互預(yù)測單一硬體架構(gòu)來增加硬體使用效率以及降低成本。
The simulation in quartusii for the blocks with fpga is proposed at last . compare with the traditional polarization diversity and combining receiver , the stability of the scheme proposed in this paper is better , the parameter of it is reprogrammable , and upgrading of the system is also easily . then the diversity 與傳統(tǒng)的極化分集接收機相比,利用本文提出的系統(tǒng)設(shè)計方案設(shè)計的數(shù)字極化分集接收機具有工作更穩(wěn)定,參數(shù)可編程以及便于系統(tǒng)升級等優(yōu)點,這樣就使得在一個硬件平臺上實現(xiàn)不同參數(shù)分集接收成為可能。
In order to resolve the contradiction between real - time and arithmetic complex in the television tracking capture system , the paper designs the real - time target track processing system which is constructed by the high performance dsp chipset tms320c6416 as the core digital processor , the huge reprogrammable logic chipset cpld as the system logic control and the field reprogrammable array fpga as the image preprocessing chipset to sampled video digital image 摘要為解決電視捕獲跟蹤瞄準系統(tǒng)中系統(tǒng)的實時性與算法復(fù)雜性之間的矛盾,設(shè)計了以高性能的dsp芯片tms320c6416為核心處理器,結(jié)合大規(guī)模可編程邏輯器件cpld進行邏輯控制以及現(xiàn)場可編程門陣列fpga對采集的視頻數(shù)字圖像做預(yù)處理的實時目標識別跟蹤處理平臺。
The real - time target track processing system is designed which is constructed by the high performance dsp chipset tms320c6416 as the core digital processor , the huge reprogrammable logic chipset cpld as the system logic control and the field reprogrammable array fpga as the image preprocessing chipset to sampled video digital image 為了解決算法復(fù)雜性及滿足工程實時性,設(shè)計了以高性能的dsp芯片tms320c6416為核心處理器,結(jié)合大規(guī)??删幊踢壿嬈骷pld進行邏輯控制以及現(xiàn)場可編程門陣列fpga對采集的視頻數(shù)字圖像做預(yù)處理的實時目標識別跟蹤處理平臺。