logic design

"logic design"的翻譯和解釋

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例句與用法

As vlsi design becomes larger and takes up much longer time , verification and debugging of logic design become the dominating part of total design period . in order to reduce the time for obtaining a valid design , many verification techniques have been studied . fpga is relatively useful in such case due to its rapid implementation
隨著現(xiàn)代vlsi設計規(guī)模迅速擴大、芯片的設計和實現(xiàn)周期變長，驗證和調試在asic設計中占有越來越重要的地位，相應的在整個asic設計流程中，驗證和調試將占用更多的時間。
We pointed out the features of this infrastructure , analyzed the basis of modern applied software - mvc mode , elaborated the j2ee system infrastructure used by this system , and analyzed the integrated infrastructure system . then from the system ' s real requirement , with the object - oriented method , we used an advanced modeling tool - rose to model the system ' s requirement and logic design , then finally implemented the system design . this system uses powerdesigner to do the data modeling , jbuilder as the development tool , and struts framework to realize the separation of the expressing layer , the logic layer and the data layer
通過研究和開發(fā)寬帶boss ，了解了有關boss的基本概念、模型、發(fā)展現(xiàn)狀及發(fā)展趨勢；然后分析了現(xiàn)代應用軟件的架構： b s架構，指出了此種架構的特點，并分析了現(xiàn)代應用軟件架構的基礎? ? mvc模式，詳細介紹了本系統(tǒng)所采用的j2ee體系架構，對組成本系統(tǒng)的整體架構體系進行分析；隨后從本系統(tǒng)的實際需求出發(fā)，以面向對象的方法，采用先進的建模工具rose對系統(tǒng)的需求及邏輯設計進行建模；最后對系統(tǒng)設計加以實現(xiàn)，本系統(tǒng)用powerdesigner對數(shù)據(jù)建模，以jbuilder為開發(fā)工具，采用struts框架實現(xiàn)表示層、邏輯層及數(shù)據(jù)層的分離，數(shù)據(jù)層采用數(shù)據(jù)持久化技術hibernate ，從而可以隱藏訪問數(shù)據(jù)源的數(shù)據(jù)訪問api ，簡化開發(fā)。
If there is such a tool , for the control logic designed in stateflow , the system engineer could provide the rtl description of the system to the ic engineer . thus , the work of programming in hdl will be omitted , and the ic engineer could have more time to the design coming - up
如果存在這樣的轉換工具,對于使用stateflow設計的控制邏輯部分,系統(tǒng)工程師可以直接向ic工程師提供系統(tǒng)的rtl描述,省去了ic工程師在硬件描述語言上的編程工作,使得他能夠將更多的精力放在后續(xù)的設計中。