processor architecture中文是什么意思

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中文翻譯
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處理機(jī)體系結(jié)構(gòu)

processor n. 1.〔美國(guó)〕農(nóng)產(chǎn)品加工者；進(jìn)行初步分類的人。 2. ...
architecture n. 1.建筑學(xué)。 2.建筑(樣式、風(fēng)格)；建筑物。 3 ...
architecture free processor 無(wú)結(jié)構(gòu)式處理機(jī); 無(wú)結(jié)構(gòu)式信息處理機(jī)
architecture scalable processor 可定標(biāo)處理器結(jié)構(gòu)
architecture, scalable processor (sparc) 可定標(biāo)處理器（體系）結(jié)構(gòu)
architecture-free processor 無(wú)結(jié)構(gòu)式處理機(jī), 結(jié)構(gòu)無(wú)關(guān)型處理機(jī); 無(wú)結(jié)構(gòu)式信息處理機(jī)
front-end processor architecture 前端處理機(jī)結(jié)構(gòu)
nonnumeric processor architecture 非數(shù)值處理機(jī)體系結(jié)構(gòu)
parallel processor architecture 并行處理機(jī)結(jié)構(gòu)
scalable processor architecture 可定標(biāo)處理器結(jié)構(gòu); 可擴(kuò)縮處理器結(jié)構(gòu)
scalable processor architecture (sparc) 可定標(biāo)處理器結(jié)構(gòu)
scalar processor architecture sparc標(biāo)量處理器結(jié)構(gòu), sparc處理器; sparc處理器
variable architecture processor 可變結(jié)構(gòu)處理機(jī); 可變結(jié)構(gòu)處理器
architecture n. 1.建筑學(xué)。 2.建筑(樣式、風(fēng)格)；建筑物。 3.構(gòu)造，結(jié)構(gòu)；【自動(dòng)化】(電子計(jì)算機(jī)的)架構(gòu)，體系結(jié)構(gòu)。 civil architecture 民用建筑。 domestic architecture 住宅建筑。 naval architecture 造船術(shù)，造船學(xué)。 the architecture of a beehive 蜂窩的結(jié)構(gòu)。
processor n. 1.〔美國(guó)〕農(nóng)產(chǎn)品加工者；進(jìn)行初步分類的人。 2.(數(shù)據(jù)等的)分理者；【自動(dòng)化】信息處理機(jī)。
processor to processor connection 處理機(jī)處理機(jī)連接
academy of architecture 建筑學(xué)會(huì)
adam architecture 亞當(dāng)式建筑
advanced architecture 現(xiàn)代建筑學(xué)
agent architecture 主體體系結(jié)構(gòu)
alu architecture 算術(shù)邏輯單位結(jié)構(gòu)
aluminium and architecture 鋁與建筑
aluminum architecture 鋁建筑學(xué)
american architecture 美國(guó)建筑
amerindian architecture 印地安人建筑

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And described three ways in detail separately : more access ports and non - blocking cache and quick hit buffer ( qhb ) , and analyzed their performance . smpdca is a promising processor architecture
并分別對(duì)更多的訪問(wèn)端口、非阻塞cache以及快速命中緩沖區(qū)( qhb )等三種方法進(jìn)行了詳細(xì)描述和性能模擬分析。
Multi - issue processors enhanced with momr units provide additional speedup over standard multi - issue processors with the same datapath . momr is a general architectural solution for word - oriented processor architectures to incorporate datarich operations
本文的一個(gè)重要貢獻(xiàn)是我們認(rèn)為快速加密處理取決于一個(gè)處理器支持復(fù)雜位級(jí)運(yùn)算和多字運(yùn)算的能力。
Then , the work researches multithread processor architecture based on the armp . this dissertation focused on the branch predictor of high performance processor and fetch unit of selective execution of multithread architecture
接著，本文以armp為基礎(chǔ)深入了解國(guó)內(nèi)外目前最先進(jìn)的多線程處理器系統(tǒng)結(jié)構(gòu)研究工作，明確了該領(lǐng)域研究的發(fā)展方向和研究難點(diǎn)。
Contain metadata that includes the version number and culture of the assembly , an optional public key that uniquely identifies the list of classes of the assembly , the methods that are defined in the assembly , and the processor architecture of the assembly
包含程序集以下方面的元數(shù)據(jù)：版本號(hào)和區(qū)域性、唯一標(biāo)識(shí)類列表的可選公鑰、定義的方法以及處理器體系結(jié)構(gòu)。
This paper describes how to establish an embedded system development platform based on multi - processor architecture . the platform consists of three components : the linux operating system , device driver program and low - level software
論文的主要工作是在多種處理器體系結(jié)構(gòu)上建立嵌入式linux系統(tǒng)的開(kāi)發(fā)平臺(tái)，包括嵌入式linux操作系統(tǒng)、驅(qū)動(dòng)程序的開(kāi)發(fā)和底層軟件的支持。
As both pseries and iseries servers are based on the same power processor architecture , binaries compiled under a linux distribution on either pseries or iseries will run on both platforms with no or minimal changes
由于pseries和iseries服務(wù)器都是基于相同的power處理器體系結(jié)構(gòu)的，因此在pseries或iseries上的linux發(fā)行版本下編譯的二進(jìn)制文件不用任何修改就可以在這兩種平臺(tái)上運(yùn)行，或者僅需稍加修改即可。
The work of this paper is as follows . 1 . analyzer multithreaded processor architecture introducing the definition of multithreaded processor and the advantage of multithread processor architecture , also including simultaneous multithreaded architecture and pre - look multithreaded architecture
本論文的研究工作包括： 1 、多線程處理器系統(tǒng)結(jié)構(gòu)的進(jìn)行分析；介紹多線程處理器的定義及其優(yōu)勢(shì)所在，同時(shí)介紹了同時(shí)多線程結(jié)構(gòu)和前瞻多線程結(jié)構(gòu)。
Nowdays , most of these rpc mechanism ca n ' t be used in these systems of distributed multi - processor architecture such as distributed router , run short of the sustain of communication middleware such as rpc , it become very complicate to develop communication program in such distributed multi - processor architecture systems
現(xiàn)在大部分rpc機(jī)制不能適用像分布式路由器這樣專用性很強(qiáng)的分布式多處理結(jié)構(gòu)的系統(tǒng)。缺少像rpc這樣的通信中間件的支持，在這些分布式多處理結(jié)構(gòu)的系統(tǒng)中進(jìn)行通信編程非常復(fù)雜。
First , this page introduce the development of embedded system and the general principle of embedded system . arm architecture is the mainstream among all sorts of processor architecture , a relatively particular study has been done about the lpc2290 microcontroller that is based on arm 7 core
然后研究了32位嵌入式系統(tǒng)應(yīng)用中占主流地位的arm處理器的體系結(jié)構(gòu),包括arm微處理器體系結(jié)構(gòu)、 arm體系結(jié)構(gòu)對(duì)操作系統(tǒng)的支持、基于arm核的芯片選擇等,并從應(yīng)用的角度分析了arm7核的lpc2290微控制器。
This dissertation prosecutes a systematic study on network processor architecture especially on the packet classification technology . network processor is one core technology of next generation network and will become the core component of new types of backbone devices such as routers and switches
網(wǎng)絡(luò)處理器etworkprocessor ，簡(jiǎn)稱np )作為推動(dòng)下一代網(wǎng)絡(luò)發(fā)展的一項(xiàng)核心技術(shù)，正越來(lái)越受到集成電路產(chǎn)業(yè)界的關(guān)注，國(guó)內(nèi)外的許多公司和研究機(jī)構(gòu)紛紛投入力量展開(kāi)相關(guān)研究。

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