- [網(wǎng)絡(luò)] 可綜合；可合成；可合成的
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synthesizable中文什么意思
例句與用法
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- written entirely in synthesizable vhdl
模型全綜合設(shè)計 - together, in this part coding the reusable and synthesizable code was deeply discussed . lastly, fpga is used to test the function of the system
同時，在這部分還對可復(fù)用可綜合代碼的編寫做了比較深入地研究與探討。 - we describe this architecture synthesizable with veriloghdl langrage in fpga . according to the specification of the fpga, we chose the optimal multiplier and adder
我們用veriloghdl對這種結(jié)構(gòu)進行基于fpga實現(xiàn)的可綜合的描述，并結(jié)合fpga的特點選擇了最佳的乘法器和加法器的設(shè)計。 - 3 ) the paper discussed the theory and the method of asic high-level synthesis : ? nalyzed the synthesizable problems of vhdl language systematically, and discussed the establishment and the implementation methods of vhdl synthesis subclasses
3)本文對asic高級綜合的理論與方法進行了深入的探討：系統(tǒng)地分析了vhdl語言的可綜合性問題，并探討了vhdl綜合子集的確立及實現(xiàn)方法。 - the thesis researches on the methodology for energy efficient soc design . soc has several design levels according to the design flow . the thesis covers on the higher levels including system level, software level, and synthesizable logic level
本文主要從可綜合的邏輯層以上的設(shè)計層次來進行soc低功耗設(shè)計方法論的研究，這些層次與工藝無關(guān)，包括系統(tǒng)設(shè)計、軟件設(shè)計和可綜合邏輯設(shè)計層次。