全定制的英文

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英文翻譯
造句

full custom

全 complete
定制 custom made; custom-tailor; ...
全定制設(shè)計(jì) full custom design
全定制集成電路 full custom ic
全定位 full normal
定制 custom made; custom-tailor; have sth. made to order; have sth. custom-made 定制家具 have furniture made to order; 屋里的家具是定制的。 the furniture in the room was made to order.; 定制電路 custom circuit; 定制服裝 creation; 定制品 article made to order
安全定時(shí)器 safety timer
全定向的 all directional interchange
全定性分析 total qualitative analysis
最大安全定值 maximum safety setting
定制, 定制的 made to order
半定制 semi-customize
定制版 customization version
定制的 bespoke; custom-built; custom-made; made to order; made-to-measure; made-to-order; tailormade; tailored
定制化 customizing the schema
定制類(lèi) custom class
定制品 article made to order; custom made
定制鞋 custom shoe; customs checking
定做, 定制 customs made
鑒定制 identifier; system of identification
定制假眼,定制的假眼 custom artificial eye
半定制路由 semicustom route
半定制母片 semicustom masterslice
半定制芯片 semicustom chip
半定制陣列 semicustom array

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例句與用法

The alu designed with the methodology of full custom can realize higher speed , lower power dissipation and smaller area , and it has great value in application and significant meaning in practice
采用全定制方法設(shè)計(jì)的算術(shù)邏輯部件速度快、功耗低、面積小,具有廣泛的應(yīng)用價(jià)值和重要的實(shí)踐意義。
The whole ftlvds chip is a combination of lvds driver , lvds receiver , serializer and deserializer . it ' s layout is implemented by the means of full - custom and half - custom mixed design approach , and the chip is taped out
Ftlvds芯片是收發(fā)模塊和串并模塊的組合，其版圖實(shí)現(xiàn)采用了全定制單元和標(biāo)準(zhǔn)單元混合的設(shè)計(jì)方法，并且進(jìn)行了投片封裝。
The full - custom method is different from the semi - custom method . most people pay their attention to the verification method of semi - custom design , and there is a lack of verification method for full - custom
全定制設(shè)計(jì)方法與半定制設(shè)計(jì)方法有較多的差異,現(xiàn)有的驗(yàn)證方法大多注重于半定制的功能驗(yàn)證方法研究,缺少全定制設(shè)計(jì)的功能驗(yàn)證方法。
X processor uses full - custom design method , includes dynamic branch prediction and super scalar technology , and its scale is very large . in order to validate the design , we must apply function verification
X微處理器是一款采用全定制設(shè)計(jì)方法設(shè)計(jì)的微處理器,處理器中包含動(dòng)態(tài)分支預(yù)測(cè)和超標(biāo)量等微體系結(jié)構(gòu)技術(shù),內(nèi)部結(jié)構(gòu)復(fù)雜,設(shè)計(jì)規(guī)模很大,對(duì)其進(jìn)行功能驗(yàn)證有很大難度。
The new method can be divided into two parts : the construction of verification model and the construction of verification platform . not like the semi - custom verification model is built from the design specification , the full - custom verification model is built from full - custom design data
對(duì)于驗(yàn)證模型的建立,在半定制設(shè)計(jì)驗(yàn)證方法中,一般是以系統(tǒng)描述為基礎(chǔ)建立驗(yàn)證模型,而在我們的全定制設(shè)計(jì)驗(yàn)證方法中,驗(yàn)證模型主要以全定制設(shè)計(jì)數(shù)據(jù)為基礎(chǔ)建立的。
Since this type of converter has little requirement for the digital parts and its digital structure is relative simple , the whole design approach of the converter is the same with the design flow of the analog circuit that is to draw schematics and layout manually , edit the drc lvs files to verify the layout and check its performance by means of post - simulation
由于本設(shè)計(jì)對(duì)數(shù)字電路部分的性能要求較寬松，而且電路結(jié)構(gòu)相對(duì)簡(jiǎn)單，所以采用和模擬電路設(shè)計(jì)一致的設(shè)計(jì)方法，即：使用原理圖輸入設(shè)計(jì)，全定制編輯版圖，對(duì)版圖進(jìn)行drc ， lvs以及后仿真驗(yàn)證。使用的是cadence中的一系列cad工具。
After having analyzed the theory of the calculator circuit thoroughly , the author made use of the characteristic of the calendar circuit and put forward a new design method , namely replacing the static circuit with the dynamic circuit to reduce the area of whole chip . now the author has finished the design of the calendar circuit and accomplished the layout design with the full - custom method
本文作者在透徹分析計(jì)算器原理的基礎(chǔ)上，利用萬(wàn)年歷電路的工作頻率的特點(diǎn)，提出了以cmos動(dòng)態(tài)門(mén)代替靜態(tài)觸發(fā)器的設(shè)計(jì)方法，獨(dú)立設(shè)計(jì)出萬(wàn)年歷部分電路，將其與計(jì)算器部分電路緊密融合，構(gòu)成一塊完整的數(shù)字大規(guī)模集成電路，并以全定制的方法實(shí)現(xiàn)了整個(gè)芯片的版圖設(shè)計(jì)。
This task of self - determination design of high speed lvds i / o interface chip , as a part of the project " high speed digital signal interlink and transmit technology " on the foundation of national laboratory for parallel & distributed processing , on the one hand provide absolutely necessarily experiment foundation and hardware elements for the research of high speed digital signal transmission , on the other hand make an available exploration for the forward design methods of ic chips by means of full - custom and half - custom mixed design approach
本課題對(duì)lvds高速i o接口單元芯片ftlvds的自主設(shè)計(jì)研究，作為國(guó)防科技重點(diǎn)實(shí)驗(yàn)室基金項(xiàng)目“高速數(shù)字信號(hào)互連與信號(hào)傳輸技術(shù)”的一部分，一方面為進(jìn)行高速數(shù)字信號(hào)傳輸?shù)难芯刻峁┝瞬豢扇鄙俚膶?shí)驗(yàn)依據(jù)和硬件基礎(chǔ)，另一方面也是對(duì)ic芯片正向設(shè)計(jì)中采用全定制和半定制的混合設(shè)計(jì)方法的一次有益探索。
Focusing on a 64 - bit high - performance general purpose microprocessor with fully independent intellectual property , the thesis investigates a 128 - word 65 - bit general register file with 12 - read and 8 - write ports which is a representational one for its large - scale and multi - port characteristics in that microprocessor , and realizes its full custom design with high speed in read and write access . from the layout simulation result , under the 0 . 18um process , the upper limit working frequency for the register file is 900mhz
本文面向一款具有完全自主知識(shí)產(chǎn)權(quán)的64位高性能通用處理器,對(duì)其中具有代表性的128字65位12讀端口和8寫(xiě)端口的通用寄存器文件進(jìn)行研究,實(shí)現(xiàn)了它的高速讀寫(xiě)全定制設(shè)計(jì),版圖模擬結(jié)果表明,在0 . 18um工藝下,設(shè)計(jì)可以工作的時(shí)鐘頻率上限為900mhz 。