It presents the verification strategy used in the whole eda design flow of the chip . the simulation on module level ( inc . post - layout ) uses the software event - driven simulator , the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator , for the gate - level netlist produced by using top - down design flow , the sta tool can analyze the static timing , and more formal verification is used to ensure the correct function 本章還提出了系統(tǒng)在整個(gè)eda設(shè)計(jì)流程中的設(shè)計(jì)驗(yàn)證策略方法:模塊級的模擬(包括布線后的模擬)全部采用事件驅(qū)動(dòng)式的軟件模擬工具來驗(yàn)證,各大模塊的聯(lián)合模擬及整個(gè)芯片的功能驗(yàn)證(寄存器傳輸級與門級)使用基于周期的模擬工具和硬件仿真器;對于采用top - down的設(shè)計(jì)方法得到的門級網(wǎng)表使用專門的靜態(tài)時(shí)序分析工具來進(jìn)行時(shí)序分析以及采用形式驗(yàn)證來保證正確的功能。